ggml-cpu:add RISC-V RVV (Zvfh) optimization for FP16 vector scaling #17314
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Signed-off-by: Wang Yang <yangwang@iscas.ac.cn>
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ggml/src/ggml-cpu/vec.h
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| #else | ||
| for (int i = 0; i < n; ++i) { | ||
| y[i] = GGML_CPU_FP32_TO_FP16(GGML_CPU_FP16_TO_FP32(y[i]) * v); | ||
| } | ||
| #endif |
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Try to reorganize the code to avoid duplicating the scalar implementaiton
ggerganov
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Nov 17, 2025
ggml/src/ggml-cpu/vec.h
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| svfloat16_t out = svmul_f16_m(pg, hy, vx); | ||
| svst1_f16(pg, (__fp16 *)(y + np), out); | ||
| } | ||
| #elif defined(GGML_SIMD) && defined(__riscv_v_intrinsic) && defined(__riscv_zvfh) |
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Do we need defined(GGML_SIMD) here?
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ggml/src/ggml-cpu/simd-mappings.h
we do not need defined(GGML_SIMD) , thank you for your reminder.
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This PR introduces vectorized support for the
ggml_vec_scale_f16function on RISC-V platforms that implement the Zvfh extension.