Try to add support code for riscv64 #49
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Hi, @seranian, Could you please approve running the CI workflow? Thank you! |
seranian
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seranian
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Hi,
See my comments in the code.
multichase.c
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| args->x.genchase_args->arena, | ||
| args->x.genchase_args->arena + args->x.genchase_args->total_memory); | ||
| #endif | ||
| #if defined(__riscv) && __riscv_xlen == 64 |
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The code within this #define is exactly the same as for the ARM64 above. Why not merge the two?
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Yes,you are right. These codes merge together better. At that time, the main concern was that these codes might need additional adjustments for RISC-V in the future. The two codes have been merged according to your suggestion.
| #if defined(__aarch64__) | ||
| asm volatile ("stnp %0, %1, [%2]" :: "r"(b[i]+c[i]), "r"(b[i+1]+c[i+1]), "r" (a+i)); | ||
| #elif defined(__riscv) && __riscv_xlen == 64 | ||
| asm volatile ("sd %0, (%2)\n\t" |
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A comment would go a long way to describe what this inline asm is supposed to do.
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sd (Store Doubleword) is a risc-v memory store instruction that stores a 64-bit (8-byte) value from a register to memory. "sd %0, (%2)\n\t" stores 64-bit value from register %0 to memory address contained in register %2, "sd %1, 8(%2)" stores 64-bit value from register %1 to memory address [%2] + 8. @seranian comments have been added.
merge risc-v and arm code.
add comment about riscv asm code.
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Add support code for riscv64, functionality tested and working on the Spacemit® X60 development board. Test logs are as follows.