New pico ice board support.... #299
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- Add BOARD_PICO_ICE configuration to LogicAnalyzer_Board_Settings.h - Add BOARD_PICO_ICE handling to CMakeLists.txt - Update LogicAnalyzer_Build_Settings.cmake to include new board option - Update SDK version to 2.2.0 for Linux compatibility - Set TURBO_MODE=0 for stability Pin configuration for pico-ice: - INPUT_PIN_BASE 2 (GPIO2-GPIO28 available for capture) - WS2812_LED on GPIO15 - Complex trigger support with GPIO0/GPIO1 - 24 channels, 100/200 MHz frequencies
- Fix SPI pin definitions to match actual pico-ice pinout (GPIO 8,11,10,9,14) - Change LED from GPIO15 (blue, WS2812) to GPIO12 (green, GPIO) to avoid capture conflicts - Set INPUT_PIN_BASE to 0 to match GPIO0-7 capture range - Add PIN_MAP definition for GPIO0-7, GPIO12-27 capture channels - Build now succeeds without errors
- Add protection for GPIO24 (FPGA clock) and GPIO27 (CRESETN) pins in all capture functions - Prevents PIO from taking ownership of critical FPGA output pins during captures - Allows monitoring these pins without interfering with FPGA operation - Maintains minimal changes approach - only protects the two critical output pins
…4/GPIO27 in trigger configuration
- Replace all pico-ice specific PIN_FPGA_CRESETN/PIN_CLOCK checks with gpio_is_dir_out() - Apply universal protection to all capture modes: Simple, Fast, Complex, Blast - Protect both pio_gpio_init() and pio_sm_set_consecutive_pindirs() calls - Preserve output pins (FPGA clocks, LEDs, etc.) while allowing monitoring - Add clear comments explaining how to revert if needed - Remove all BUILD_PICO_ICE conditional compilation from capture logic - Solution works for any board with output pins, not just pico-ice
…utting output pins into high-Z state after capture completion
- Add BOARD_PICO_ICE configuration with FPGA control pins - Implement FPGA initialization: CRESETN control, CDONE monitoring, 10MHz PIO clock - Add universal pin state preservation during/after capture operations - Create complete pico-ice documentation with channel mapping - Preserve all pin states (input/output/high-Z) for Core 1 user applications - Maintain FPGA clock and reset signals throughout capture operations
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The pico-ice is a board for FPGA development that uses the RP2040 to load the FPGA CRAM and supply the FPGA clock. This pull request makes it so the RP2040 can also be used as a logic analyzer to debug the FPGA, and if using the RP2040 in the project is desired, core 1 is available for the user.