| Area | Focus |
|---|---|
| AI Hardware | FPGA NPU, systolic array datapaths, custom ISA, memory hierarchy |
| LLM Inference | Transformer decode bottlenecks, KV-cache, GEMM/GEMV, quantization |
| Systems | C/C++, Python runtimes, queues, profiling, reproducible benchmarks |
| Research Writing | Paper notes, architecture diagrams, experiment logs, technical reports |
|
INT4 quantized FPGA NPU for LLM inference on Xilinx KV260. |
Lightweight LLM inference engine with INT4 / INT16 quantization. |
|
Tauri + React inference visualization and trace inspector. |
Research notebook and ISA documentation for the pccx project family. |
I am building a research-oriented AI systems portfolio around edge LLM inference, where model graphs meet memory bandwidth, runtime queues, quantization, and hardware limits.
- Main stack: SystemVerilog / FPGA / C++ / Python / TypeScript
- Main research theme: memory-bound Transformer inference
- Main project family: pccx / pccx-lab / llm-bottleneck-lab
- Homepage: technical notebook + project portfolio + paper notes
About this website repository
This repository also contains my personal website and research notebook, built with Docusaurus and customized as a quiet, text-first engineer notebook.
npm run start
npm run buildThe website is used as a technical portfolio for AI systems, FPGA acceleration, LLM inference experiments, research notes, and project documentation.



