Q1: Implement a 4-bit register using D flip-flops.
Solution Code:
Testbench Code:
Q2: Implement an 8-bit register using behavioral modeling with a single read and write port such that both read and write operations can occur simultaneously, but when they do read is given more priority.
Solution Code:
Testbench Code:
Q3: Implement an 8-bit SISO shift register using behavioral modeling.
Solution Code:
Testbench Code:
Q4: Implement an 8-bit SIPO shift register using behavioral modeling.
Q5: Implement an 8-bit PISO shift register using behavioral modeling.
Q6: Implement an 8-bit PIPO shift register using behavioral modeling.
Q7: Implement an 8-bit register with 1 read port and 2 write ports. Either read or write is permitted at a time and when you perform write, you are to write through the two write ports alternately.
Q8: Implement an 8-bit register file with 8 registers such that only a read or write can oc cur at a time.
Q9: Implement a 64-bit register file with 32 register with 4 read ports and 2 write ports. Multiple operations can occur at a time, but the lower port is given more priority in such cases. Read > Write .
Q10: Implement a 4-bit universal shift register.
To understand the context of the sample codes, refer to the Registers Documentation.