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@bibrak bibrak commented Aug 15, 2025

Provides implmentation of getAtomicAccessAttribute using system allocator.
Completes the implementation of the madvise feature using the new IOCTLs in xe_drm header.

bibrak added 4 commits August 15, 2025 12:19
Provides implmentation of getAtomicAccessAttribute using system
allocator.
Completes the implementation of the madvise feature using the
new IOCTLs in xe_drm header.

Signed-off-by: Chandio, Bibrak Qamar <bibrak.qamar.chandio@intel.com>
Provides implmentation of getAtomicAccessAttribute using system
allocator.
Completes the implementation of the madvise feature using the
new IOCTLs in xe_drm header.

Signed-off-by: Chandio, Bibrak Qamar <bibrak.qamar.chandio@intel.com>
Provides implmentation of getAtomicAccessAttribute using system
allocator.
Completes the implementation of the madvise feature using the
new IOCTLs in xe_drm header.

Signed-off-by: Chandio, Bibrak Qamar <bibrak.qamar.chandio@intel.com>
Provides implmentation of getAtomicAccessAttribute using system
allocator.
Completes the implementation of the madvise feature using the
new IOCTLs in xe_drm header.

Signed-off-by: Chandio, Bibrak Qamar <bibrak.qamar.chandio@intel.com>
@bibrak bibrak changed the title [Do Not Merge] feature: Complete madvise for System Allocator feature: Complete madvise for System Allocator Aug 19, 2025
@bibrak bibrak marked this pull request as ready for review August 19, 2025 08:33
default:
return false;
}
uint64_t param = (static_cast<uint64_t>(atomicParam) << 32) | 0;
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why we need to do those shifts after returning the value from iocthHelper?
IoctlHelper should rather do this translation internally if needed.
Also what is the point of | 0 ?

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ioctlHelper->getAtomicAccess(mode); returns 32bit int. Therefore, it is needed to shift it to the left since param needs to be 64bit containing two 32bit values. I will remove the | 0 its not needed.

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you can change it to 64 bit

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Its being used in many other places especially for legacy i915. That will require major refactoring.

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we need it anyway, as right now you need to do those shifts, which requires helper function

auto ioctlHelper = drm.getIoctlHelper();

// Apply the shared system USM IOCTL to all the VMs of the device
std::vector<uint32_t> vmIds;
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please use StackVec

return true;
}

AtomicAccessMode IoctlHelperXe::getVmSharedSystemAtomicAttribute(uint64_t handle, const size_t size, const std::vector<uint32_t> &vmIds) {
std::string vmIdsStr = "[";
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do not create string just for purpose of logging
this would cause overhead even if logging is disabled

query.vm_id, query.start, query.range, query.num_mem_ranges, query.sizeof_mem_range_attr, ret);

struct drm_xe_mem_range_attr *attr = (struct drm_xe_mem_range_attr *)ptr;
uint32_t val = attr->atomic.val;
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what's the point of passing / allocating multiple ranges if atomic attribute is extracted only from the first one ?

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Currently, the L0 Spec is such that the user provides a range and expects a single atomic attribute.

https://oneapi-src.github.io/level-zero-spec/level-zero/latest/core/api.html#zememsetatomicaccessattributeexp

There is no notion of user providing a range to zeMemSetAtomicAccessAttributeExp (in the form of const void *ptr, size_t size pair) that contains multiple ranges and therefore expects the return of multiple attributes.

So, this PR assumes that when the user calls zeMemSetAtomicAccessAttributeExp the call is made on a single allocation with the entire range having a single atomic attribute.

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yes, can we have similar simple IOCTL call with just one range?

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2 participants