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Add SM3, SM4 detection on x86 #157

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Merged
klauspost merged 1 commit into from
Mar 19, 2025
+88 −80
Merged

Add SM3, SM4 detection on x86 #157

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2 changes: 2 additions & 0 deletions README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -421,6 +421,8 @@ Exit Code 1
| SHA | Intel SHA Extensions |
| SME | AMD Secure Memory Encryption supported |
| SME_COHERENT | AMD Hardware cache coherency across encryption domains enforced |
| SM3_X86 | SM3 instructions |
| SM4_X86 | SM4 instructions |
| SPEC_CTRL_SSBD | Speculative Store Bypass Disable |
| SRBDS_CTRL | SRBDS mitigation MSR available |
| SSE | SSE functions |
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4 changes: 4 additions & 0 deletions cpuid.go
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Expand Up @@ -223,6 +223,8 @@ const (
SHA // Intel SHA Extensions
SME // AMD Secure Memory Encryption supported
SME_COHERENT // AMD Hardware cache coherency across encryption domains enforced
SM3_X86 // SM3 instructions
SM4_X86 // SM4 instructions
SPEC_CTRL_SSBD // Speculative Store Bypass Disable
SRBDS_CTRL // SRBDS mitigation MSR available
SRSO_MSR_FIX // Indicates that software may use MSR BP_CFG[BpSpecReduce] to mitigate SRSO.
Expand Down Expand Up @@ -1280,6 +1282,8 @@ func support() flagSet {
// CPUID.(EAX=7, ECX=1).EAX
eax1, _, _, edx1 := cpuidex(7, 1)
fs.setIf(fs.inSet(AVX) && eax1&(1<<4) != 0, AVXVNNI)
fs.setIf(eax1&(1<<1) != 0, SM3_X86)
fs.setIf(eax1&(1<<2) != 0, SM4_X86)
fs.setIf(eax1&(1<<7) != 0, CMPCCXADD)
fs.setIf(eax1&(1<<10) != 0, MOVSB_ZL)
fs.setIf(eax1&(1<<11) != 0, STOSB_SHORT)
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162 changes: 82 additions & 80 deletions featureid_string.go
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