Digital Systems Design

106.2 數位系統設計課程作業（Verilog/Quartus/ModelSim）

Overview

This repository contains homework/lab projects for a Digital Systems Design course. Each assignment is a Verilog-based project with its own testbench, simulation setup (ModelSim), and Quartus project files for synthesis and FPGA programming.

Repository structure

• hhw1/ — Homework 1 project (Quartus project, Verilog sources, testbench, simulation setup)
• hhw2/ — Homework 2 project
• hw3/ — Homework 3 project
• hw4/ — Homework 4 project
• README.md — This document

Typical contents inside each hw* directory:

• Verilog sources: e.g., counter.v, hw2.v, hw3.v, hw4.v, helper modules
• Testbenches: e.g., hw1_tb.v, hw2_tb.v, hw3_tb.v, hw4_tb.v
• Quartus project files: *.qpf, *.qsf
• ModelSim setup: simulation/modelsim/ with *.do scripts
• Build artifacts: output_files/, incremental_db/ (can be regenerated)

Requirements

• Intel Quartus Prime (Lite/Standard) with supported device family
• ModelSim (Intel FPGA Edition) or QuestaSim for simulation
• A supported FPGA board if you plan to program hardware (optional)

Quick start — simulate

You can run simulations using ModelSim/Questa. From the GUI:

1. Open ModelSim.
2. Change directory to the target project folder, e.g. hhw1/simulation/modelsim.
3. Run the provided script, for example: do hhw1_run_msim_rtl_verilog.do.

From a shell, a typical pattern is:

cd hhw1/simulation/modelsim
vsim -do hhw1_run_msim_rtl_verilog.do

Adjust the folder/script names for hhw2, hw3, or hw4 as needed.

Build and program — Quartus

1. Open Quartus and open the corresponding *.qpf (e.g., hhw1.qpf).
2. Set the correct device if prompted.
3. Compile the project (Analysis & Synthesis → Fitter → Assembler).
4. Use the Programmer to load the generated .sof from output_files/ to your FPGA board.

Notes

• The output_files/ and incremental_db/ directories are generated by tools and can be removed and regenerated by Quartus.
• Testbenches are provided for each assignment to verify functionality before synthesis.
• Some folders include vendor/IP models or datasheets used by the labs.

Language

The code and file names are primarily in English, while some documents and comments may be in Chinese to match the course materials.

License

No explicit license is provided. If you intend to reuse code, please contact the author or add an appropriate license file.