Skip to content

Conversation

zzSunil
Copy link

@zzSunil zzSunil commented Aug 29, 2025

Fix the issue where using intrinsics generated atomic load/store instructions on RISC-V caused SEGFAULT when accessing MMIO regions, by adding a RISC-V specific implementation to resolve the problem.

Tested on SG2044 with MT28908 RDMA(mlx5) card.

@zzSunil zzSunil force-pushed the master branch 12 times, most recently from 4fae60d to 3f62b56 Compare August 29, 2025 10:43
Fix the issue where using intrinsics to generate
atomic load/store instructions on RISC-V caused
SEGFAULT when accessing MMIO regions, by adding
a RISC-V specific implementation to resolve the
problem.

Signed-off-by: Zheng Zhang <zhangzheng@iscas.ac.cn>
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

1 participant