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release/21.x: Mips: Improve MipsAsmParser::expandDivRem (#172967) #173321

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release/21.x: Mips: Improve MipsAsmParser::expandDivRem (#172967) #173321

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66 changes: 15 additions & 51 deletions llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -68,6 +68,7 @@ class MCInstrInfo;
} // end namespace llvm

extern cl::opt<bool> EmitJalrReloc;
extern cl::opt<bool> NoZeroDivCheck;

namespace {

Expand Down Expand Up @@ -4230,7 +4231,7 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
if (!ATReg)
return true;

if (ImmValue == 0) {
if (!NoZeroDivCheck && ImmValue == 0) {
if (UseTraps)
TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI);
else
Expand Down Expand Up @@ -4262,7 +4263,7 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
// break, insert the trap/break and exit. This gives a different result to
// GAS. GAS has an inconsistency/missed optimization in that not all cases
// are handled equivalently. As the observed behaviour is the same, we're ok.
if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64) {
if (!NoZeroDivCheck && (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64)) {
if (UseTraps) {
TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI);
return false;
Expand All @@ -4283,62 +4284,25 @@ bool MipsAsmParser::expandDivRem(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out,
MCSymbol *BrTarget;
MCOperand LabelOp;

if (UseTraps) {
TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
} else {
// Branch to the li instruction.
BrTarget = Context.createTempSymbol();
LabelOp = MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context));
TOut.emitRRX(Mips::BNE, RtReg, ZeroReg, LabelOp, IDLoc, STI);
}

TOut.emitRR(DivOp, RsReg, RtReg, IDLoc, STI);
if (!NoZeroDivCheck) {
if (UseTraps) {
TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
} else {
// Branch to the li instruction.
BrTarget = Context.createTempSymbol();
LabelOp =
MCOperand::createExpr(MCSymbolRefExpr::create(BrTarget, Context));
TOut.emitRRX(Mips::BNE, RtReg, ZeroReg, LabelOp, IDLoc, STI);
}

if (!UseTraps)
TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
if (!UseTraps)
TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);

if (!Signed) {
if (!UseTraps)
TOut.getStreamer().emitLabel(BrTarget);

TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI);
return false;
}

MCRegister ATReg = getATReg(IDLoc);
if (!ATReg)
return true;

if (!UseTraps)
TOut.getStreamer().emitLabel(BrTarget);

TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI);

// Temporary label for the second branch target.
MCSymbol *BrTargetEnd = Context.createTempSymbol();
MCOperand LabelOpEnd =
MCOperand::createExpr(MCSymbolRefExpr::create(BrTargetEnd, Context));

// Branch to the mflo instruction.
TOut.emitRRX(Mips::BNE, RtReg, ATReg, LabelOpEnd, IDLoc, STI);

if (IsMips64) {
TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI);
TOut.emitDSLL(ATReg, ATReg, 63, IDLoc, STI);
} else {
TOut.emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, STI);
}

if (UseTraps)
TOut.emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, STI);
else {
// Branch to the mflo instruction.
TOut.emitRRX(Mips::BNE, RsReg, ATReg, LabelOpEnd, IDLoc, STI);
TOut.emitNop(IDLoc, STI);
TOut.emitII(Mips::BREAK, 0x6, 0, IDLoc, STI);
}

TOut.getStreamer().emitLabel(BrTargetEnd);
TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI);
return false;
}
Expand Down
4 changes: 4 additions & 0 deletions llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,10 @@ cl::opt<bool>
EmitJalrReloc("mips-jalr-reloc", cl::Hidden,
cl::desc("MIPS: Emit R_{MICRO}MIPS_JALR relocation with jalr"),
cl::init(true));
cl::opt<bool>
NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
cl::desc("MIPS: Don't trap on integer division by zero."),
cl::init(false));

namespace {
static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
Expand Down
6 changes: 1 addition & 5 deletions llvm/lib/Target/Mips/MipsISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -81,12 +81,8 @@ using namespace llvm;

STATISTIC(NumTailCalls, "Number of tail calls");

static cl::opt<bool>
NoZeroDivCheck("mno-check-zero-division", cl::Hidden,
cl::desc("MIPS: Don't trap on integer division by zero."),
cl::init(false));

extern cl::opt<bool> EmitJalrReloc;
extern cl::opt<bool> NoZeroDivCheck;

static const MCPhysReg Mips64DPRegs[8] = {
Mips::D12_64, Mips::D13_64, Mips::D14_64, Mips::D15_64,
Expand Down
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