[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental #173331

svs-quic · 2025-12-23T02:57:29Z

Version 0.13 of the Xqci Qualcomm uC Vendor Extension has been marked as frozen. We've had assembler support for this since LLVM20 and code generation support since LLVM21. I think we have enough coverage in the code base to mark the extension as non-experimental.

llvmbot · 2025-12-23T02:57:59Z

@llvm/pr-subscribers-debuginfo

@llvm/pr-subscribers-backend-risc-v

Author: Sudharsan Veeravalli (svs-quic)

Changes

Version 0.13 of the Xqci Qualcomm uC Vendor Extension has been marked as frozen. We've had assembler support for this since LLVM20 and code generation support since LLVM21. I think we have enough coverage in the code base to mark the extension as non-experimental.

Patch is 159.37 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/173331.diff

98 Files Affected:

(modified) clang/test/Driver/print-supported-extensions-riscv.c (+19-19)
(modified) llvm/docs/RISCVUsage.rst (+21-18)
(modified) llvm/docs/ReleaseNotes.md (+1)
(modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+39-42)
(modified) llvm/test/CodeGen/RISCV/attributes-qc.ll (+18-18)
(modified) llvm/test/CodeGen/RISCV/cmov-branch-opt.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/codemodel-lowering.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/features-info.ll (+19-19)
(modified) llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/i32-icmp.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/imm.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/jumptable.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/make-compressible-xqci.mir (+4-4)
(modified) llvm/test/CodeGen/RISCV/min-max.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/pr148084.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/select-bare.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/select-cc.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/select-cond.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/select-const.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/select.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/short-forward-branch-load-imm.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/short-forward-branch-opt-qcloads.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/stack-offset.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/xqcia.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/xqciac.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/xqcibi.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/xqcibm-extract.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/xqcibm-insbi.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/xqcibm-insert.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/xqcicli.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/xqcicm.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/xqcics.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/xqcilia.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/xqcilo.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/xqcilsm-lwmi-swmi.mir (+1-1)
(modified) llvm/test/CodeGen/RISCV/xqcilsm-memset.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/xqcisls.ll (+1-1)
(modified) llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll (+3-3)
(modified) llvm/test/MC/Disassembler/RISCV/branch-targets-xqci.txt (+2-2)
(modified) llvm/test/MC/Disassembler/RISCV/xqci-invalid.txt (+2-2)
(modified) llvm/test/MC/RISCV/insn_xqci.s (+1-1)
(modified) llvm/test/MC/RISCV/rv32-relaxation-xqci.s (+3-3)
(modified) llvm/test/MC/RISCV/vendor-symbol.s (+1-1)
(modified) llvm/test/MC/RISCV/xqci-fixups.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcia-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcia-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqciac-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqciac-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcibi-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcibi-linker-relaxation.s (+1-1)
(modified) llvm/test/MC/RISCV/xqcibi-long-conditional-jump.s (+4-4)
(modified) llvm/test/MC/RISCV/xqcibi-relocations.s (+3-3)
(modified) llvm/test/MC/RISCV/xqcibi-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcibm-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcibm-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcicli-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcicli-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcicm-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcicm-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcics-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcics-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcicsr-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcicsr-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqciint-csrs-invalid.s (+63-63)
(modified) llvm/test/MC/RISCV/xqciint-csrs-valid.s (+3-3)
(modified) llvm/test/MC/RISCV/xqciint-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqciint-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqciio-aliases-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqciio-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqciio-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcilb-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcilb-relocations.s (+3-3)
(modified) llvm/test/MC/RISCV/xqcilb-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcili-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcili-li.s (+1-1)
(modified) llvm/test/MC/RISCV/xqcili-linker-relaxation.s (+1-1)
(modified) llvm/test/MC/RISCV/xqcili-relocations.s (+3-3)
(modified) llvm/test/MC/RISCV/xqcili-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcilia-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcilia-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcilo-aliases-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcilo-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcilo-pseudos-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcilo-pseudos-valid.s (+1-1)
(modified) llvm/test/MC/RISCV/xqcilo-valid.s (+12-12)
(modified) llvm/test/MC/RISCV/xqcilsm-aliases-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcilsm-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcilsm-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcisim-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcisim-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcisls-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcisls-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcisync-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcisync-valid.s (+6-6)
(modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+19-19)

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index bcc00d072c2ae..4be310244715e 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -178,6 +178,25 @@
 // CHECK-NEXT:     xmipscmov            1.0       'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov))
 // CHECK-NEXT:     xmipsexectl          1.0       'XMIPSEXECTL' (MIPS execution control)
 // CHECK-NEXT:     xmipslsp             1.0       'XMIPSLSP' (MIPS optimization for hardware load-store bonding)
+// CHECK-NEXT:     xqci                 0.13      'Xqci' (Qualcomm uC Extension)
+// CHECK-NEXT:     xqcia                0.7       'Xqcia' (Qualcomm uC Arithmetic Extension)
+// CHECK-NEXT:     xqciac               0.3       'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)
+// CHECK-NEXT:     xqcibi               0.2       'Xqcibi' (Qualcomm uC Branch Immediate Extension)
+// CHECK-NEXT:     xqcibm               0.8       'Xqcibm' (Qualcomm uC Bit Manipulation Extension)
+// CHECK-NEXT:     xqcicli              0.3       'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)
+// CHECK-NEXT:     xqcicm               0.2       'Xqcicm' (Qualcomm uC Conditional Move Extension)
+// CHECK-NEXT:     xqcics               0.2       'Xqcics' (Qualcomm uC Conditional Select Extension)
+// CHECK-NEXT:     xqcicsr              0.4       'Xqcicsr' (Qualcomm uC CSR Extension)
+// CHECK-NEXT:     xqciint              0.10      'Xqciint' (Qualcomm uC Interrupts Extension)
+// CHECK-NEXT:     xqciio               0.1       'Xqciio' (Qualcomm uC External Input Output Extension)
+// CHECK-NEXT:     xqcilb               0.2       'Xqcilb' (Qualcomm uC Long Branch Extension)
+// CHECK-NEXT:     xqcili               0.2       'Xqcili' (Qualcomm uC Load Large Immediate Extension)
+// CHECK-NEXT:     xqcilia              0.2       'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
+// CHECK-NEXT:     xqcilo               0.3       'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
+// CHECK-NEXT:     xqcilsm              0.6       'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
+// CHECK-NEXT:     xqcisim              0.2       'Xqcisim' (Qualcomm uC Simulation Hint Extension)
+// CHECK-NEXT:     xqcisls              0.2       'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
+// CHECK-NEXT:     xqcisync             0.3       'Xqcisync' (Qualcomm uC Sync Delay Extension)
 // CHECK-NEXT:     xsfcease             1.0       'XSfcease' (SiFive sf.cease Instruction)
 // CHECK-NEXT:     xsfmm128t            0.6       'XSfmm128t' (TE=128 configuration)
 // CHECK-NEXT:     xsfmm16t             0.6       'XSfmm16t' (TE=16 configuration)
@@ -230,25 +249,6 @@
 // CHECK-NEXT:     smpmpmt              0.6       'Smpmpmt' (PMP-based Memory Types Extension)
 // CHECK-NEXT:     svukte               0.3       'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
 // CHECK-NEXT:     xqccmp               0.3       'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)
-// CHECK-NEXT:     xqci                 0.13      'Xqci' (Qualcomm uC Extension)
-// CHECK-NEXT:     xqcia                0.7       'Xqcia' (Qualcomm uC Arithmetic Extension)
-// CHECK-NEXT:     xqciac               0.3       'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)
-// CHECK-NEXT:     xqcibi               0.2       'Xqcibi' (Qualcomm uC Branch Immediate Extension)
-// CHECK-NEXT:     xqcibm               0.8       'Xqcibm' (Qualcomm uC Bit Manipulation Extension)
-// CHECK-NEXT:     xqcicli              0.3       'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)
-// CHECK-NEXT:     xqcicm               0.2       'Xqcicm' (Qualcomm uC Conditional Move Extension)
-// CHECK-NEXT:     xqcics               0.2       'Xqcics' (Qualcomm uC Conditional Select Extension)
-// CHECK-NEXT:     xqcicsr              0.4       'Xqcicsr' (Qualcomm uC CSR Extension)
-// CHECK-NEXT:     xqciint              0.10      'Xqciint' (Qualcomm uC Interrupts Extension)
-// CHECK-NEXT:     xqciio               0.1       'Xqciio' (Qualcomm uC External Input Output Extension)
-// CHECK-NEXT:     xqcilb               0.2       'Xqcilb' (Qualcomm uC Long Branch Extension)
-// CHECK-NEXT:     xqcili               0.2       'Xqcili' (Qualcomm uC Load Large Immediate Extension)
-// CHECK-NEXT:     xqcilia              0.2       'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
-// CHECK-NEXT:     xqcilo               0.3       'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
-// CHECK-NEXT:     xqcilsm              0.6       'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
-// CHECK-NEXT:     xqcisim              0.2       'Xqcisim' (Qualcomm uC Simulation Hint Extension)
-// CHECK-NEXT:     xqcisls              0.2       'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
-// CHECK-NEXT:     xqcisync             0.3       'Xqcisync' (Qualcomm uC Sync Delay Extension)
 // CHECK-NEXT:     xrivosvisni          0.1       'XRivosVisni' (Rivos Vector Integer Small New)
 // CHECK-NEXT:     xrivosvizip          0.1       'XRivosVizip' (Rivos Vector Register Zips)
 // CHECK-NEXT:     xsfmclic             0.1       'XSfmclic' (SiFive CLIC Machine-mode CSRs)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 1e55fea9e1eb8..df5a595e8ec93 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -463,58 +463,61 @@ The current vendor extensions supported are:
 ``experimental-Xqccmp``
   LLVM implements `version 0.3 of the 16-bit Push/Pop instructions and double-moves extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.3.0>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification.
 
-``experimental-Xqcia``
+``Xqci``
+  LLVM implements `version 0.13 of the Qualcomm uC extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
+
+``Xqcia``
   LLVM implements `version 0.7 of the Qualcomm uC Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqciac``
+``Xqciac``
   LLVM implements `version 0.3 of the Qualcomm uC Load-Store Address Calculation extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcibi``
+``Xqcibi``
   LLVM implements `version 0.2 of the Qualcomm uC Branch Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcibm``
+``Xqcibm``
   LLVM implements `version 0.8 of the Qualcomm uC Bit Manipulation extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcicli``
+``Xqcicli``
   LLVM implements `version 0.3 of the Qualcomm uC Conditional Load Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcicm``
+``Xqcicm``
   LLVM implements `version 0.2 of the Qualcomm uC Conditional Move extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcics``
+``Xqcics``
   LLVM implements `version 0.2 of the Qualcomm uC Conditional Select extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcicsr``
+``Xqcicsr``
   LLVM implements `version 0.4 of the Qualcomm uC CSR extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqciint``
+``Xqciint``
   LLVM implements `version 0.10 of the Qualcomm uC Interrupts extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqciio``
+``Xqciio``
   LLVM implements `version 0.1 of the Qualcomm uC External Input Output extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcilb``
+``Xqcilb``
   LLVM implements `version 0.2 of the Qualcomm uC Long Branch extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcili``
+``Xqcili``
   LLVM implements `version 0.2 of the Qualcomm uC Load Large Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcilia``
+``Xqcilia``
   LLVM implements `version 0.2 of the Qualcomm uC Large Immediate Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcilo``
+``Xqcilo``
   LLVM implements `version 0.3 of the Qualcomm uC Large Offset Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcilsm``
+``Xqcilsm``
   LLVM implements `version 0.6 of the Qualcomm uC Load Store Multiple extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcisim``
+``Xqcisim``
   LLVM implements `version 0.2 of the Qualcomm uC Simulation Hint extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcisls``
+``Xqcisls``
   LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcisync``
+``Xqcisync``
   LLVM implements `version 0.3 of the Qualcomm uC Sync Delay extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
 ``Xmipscbop``
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 503cf641a221f..910a50214df2f 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -158,6 +158,7 @@ Changes to the RISC-V Backend
 * Adds assembler support for the Andes `XAndesvsinth` (Andes Vector Small Int Handling Extension).
 * DWARF fission is now compatible with linker relaxations, allowing `-gsplit-dwarf` and `-mrelax`
   to be used together when building for the RISC-V platform.
+* The Xqci Qualcomm uC Vendor Extension is no longger marked as experimental.
 
 Changes to the WebAssembly Backend
 ----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 3a76ac6351fdf..66e1b18f37392 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1497,47 +1497,46 @@ def HasVendorXqccmp
                          "'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)">;
 
 def FeatureVendorXqcia
-    : RISCVExperimentalExtension<0, 7, "Qualcomm uC Arithmetic Extension">;
+    : RISCVExtension<0, 7, "Qualcomm uC Arithmetic Extension">;
 def HasVendorXqcia
     : Predicate<"Subtarget->hasVendorXqcia()">,
       AssemblerPredicate<(all_of FeatureVendorXqcia),
                          "'Xqcia' (Qualcomm uC Arithmetic Extension)">;
 
 def FeatureVendorXqciac
-    : RISCVExperimentalExtension<0, 3, "Qualcomm uC Load-Store Address Calculation Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 3, "Qualcomm uC Load-Store Address Calculation Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqciac
     : Predicate<"Subtarget->hasVendorXqciac()">,
       AssemblerPredicate<(all_of FeatureVendorXqciac),
                          "'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)">;
 
 def FeatureVendorXqcibi
-    : RISCVExperimentalExtension<0, 2, "Qualcomm uC Branch Immediate Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 2, "Qualcomm uC Branch Immediate Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqcibi
     : Predicate<"Subtarget->hasVendorXqcibi()">,
       AssemblerPredicate<(all_of FeatureVendorXqcibi),
                          "'Xqcibi' (Qualcomm uC Branch Immediate Extension)">;
 
 def FeatureVendorXqcibm
-    : RISCVExperimentalExtension<0, 8, "Qualcomm uC Bit Manipulation Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 8, "Qualcomm uC Bit Manipulation Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqcibm
     : Predicate<"Subtarget->hasVendorXqcibm()">,
       AssemblerPredicate<(all_of FeatureVendorXqcibm),
                          "'Xqcibm' (Qualcomm uC Bit Manipulation Extension)">;
 
 def FeatureVendorXqcicli
-    : RISCVExperimentalExtension<0, 3,
-                                 "Qualcomm uC Conditional Load Immediate Extension">;
+    : RISCVExtension<0, 3, "Qualcomm uC Conditional Load Immediate Extension">;
 def HasVendorXqcicli
     : Predicate<"Subtarget->hasVendorXqcicli()">,
       AssemblerPredicate<(all_of FeatureVendorXqcicli),
                          "'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)">;
 
 def FeatureVendorXqcicm
-    : RISCVExperimentalExtension<0, 2, "Qualcomm uC Conditional Move Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 2, "Qualcomm uC Conditional Move Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqcicm
     : Predicate<"Subtarget->hasVendorXqcicm()">,
       AssemblerPredicate<(all_of FeatureVendorXqcicm),
@@ -1546,7 +1545,7 @@ def NoVendorXqcicm
     : Predicate<"!Subtarget->hasVendorXqcicm()">;
 
 def FeatureVendorXqcics
-    : RISCVExperimentalExtension<0, 2, "Qualcomm uC Conditional Select Extension">;
+    : RISCVExtension<0, 2, "Qualcomm uC Conditional Select Extension">;
 def HasVendorXqcics
     : Predicate<"Subtarget->hasVendorXqcics()">,
       AssemblerPredicate<(all_of FeatureVendorXqcics),
@@ -1555,102 +1554,100 @@ def NoVendorXqcics
     : Predicate<"!Subtarget->hasVendorXqcics()">;
 
 def FeatureVendorXqcicsr
-    : RISCVExperimentalExtension<0, 4, "Qualcomm uC CSR Extension">;
+    : RISCVExtension<0, 4, "Qualcomm uC CSR Extension">;
 def HasVendorXqcicsr
     : Predicate<"Subtarget->hasVendorXqcicsr()">,
       AssemblerPredicate<(all_of FeatureVendorXqcicsr),
                          "'Xqcicsr' (Qualcomm uC CSR Extension)">;
 
 def FeatureVendorXqciint
-    : RISCVExperimentalExtension<0, 10, "Qualcomm uC Interrupts Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 10, "Qualcomm uC Interrupts Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqciint
     : Predicate<"Subtarget->hasVendorXqciint()">,
       AssemblerPredicate<(all_of FeatureVendorXqciint),
                          "'Xqciint' (Qualcomm uC Interrupts Extension)">;
 
 def FeatureVendorXqciio
-    : RISCVExperimentalExtension<0, 1, "Qualcomm uC External Input Output Extension">;
+    : RISCVExtension<0, 1, "Qualcomm uC External Input Output Extension">;
 def HasVendorXqciio
     : Predicate<"Subtarget->hasVendorXqciio()">,
       AssemblerPredicate<(all_of FeatureVendorXqciio),
                          "'Xqciio' (Qualcomm uC External Input Output Extension)">;
 
 def FeatureVendorXqcilb
-    : RISCVExperimentalExtension<0, 2, "Qualcomm uC Long Branch Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 2, "Qualcomm uC Long Branch Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqcilb
     : Predicate<"Subtarget->hasVendorXqcilb()">,
       AssemblerPredicate<(all_of FeatureVendorXqcilb),
                          "'Xqcilb' (Qualcomm uC Long Branch Extension)">;
 
 def FeatureVendorXqcili
-    : RISCVExperimentalExtension<0, 2, "Qualcomm uC Load Large Immediate Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 2, "Qualcomm uC Load Large Immediate Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqcili
     : Predicate<"Subtarget->hasVendorXqcili()">,
       AssemblerPredicate<(all_of FeatureVendorXqcili),
                          "'Xqcili' (Qualcomm uC Load Large Immediate Extension)">;
 
 def FeatureVendorXqcilia
-    : RISCVExperimentalExtension<0, 2, "Qualcomm uC Large Immediate Arithmetic Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 2, "Qualcomm uC Large Immediate Arithmetic Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqcilia
     : Predicate<"Subtarget->hasVendorXqcilia()">,
       AssemblerPredicate<(all_of FeatureVendorXqcilia),
                          "'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)">;
 
 def FeatureVendorXqcilo
-    : RISCVExperimentalExtension<0, 3, "Qualcomm uC Large Offset Load Store Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 3, "Qualcomm uC Large Offset Load Store Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqcilo
     : Predicate<"Subtarget->hasVendorXqcilo()">,
       AssemblerPredicate<(all_of FeatureVendorXqcilo),
                          "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)">;
 
 def FeatureVendorXqcilsm
-    : RISCVExperimentalExtension<0, 6,
-                                 "Qualcomm uC Load Store Multiple Extension">;
+    : RISCVExtension<0, 6, "Qualcomm uC Load Store Multiple Extension">;
 def HasVendorXqcilsm
     : Predicate<"Subtarget->hasVendorXqcilsm()">,
       AssemblerPredicate<(all_of FeatureVendorXqcilsm),
                          "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)">;
 
 def FeatureVendorXqcisim
-    : RISCVExperimentalExtension<0, 2, "Qualcomm uC Simulation Hint Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 2, "Qualcomm uC Simulation Hint Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqcisim
     : Predicate<"Subtarget->hasVendorXqcisim()">,
       AssemblerPredicate<(all_of FeatureVendorXqcisim),
                          "'Xqcisim' (Qualcomm uC Simulation Hint Extension)">;
 
 def FeatureVendorXqcisls
-    : RISCVExperimentalExtension<0, 2,
-                                 "Qualcomm uC Scaled Load Store Extension">;
+    : RISCVExtension<0, 2, "Qualcomm uC Scaled Load Store Extension">;
 def HasVendorXqcisls
     : Predicate<"Subtarget->hasVendorXqcisls()">,
       AssemblerPredicate<(all_of FeatureVendorXqcisls),
                          "'Xqcisls' (Qualcomm uC Scaled Load Store Extension)">;
 
 def FeatureVendorXqcisync
-    : RISCVExperimentalExtension<0, 3, "Qualcomm uC Sync Delay Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 3, "Qualcomm uC Sync Delay Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqcisync
     : Predicate<"Subtarget->hasVendorXqcisync()">,
       AssemblerPredicate<(all_of FeatureVendorXqcisync),
                          "'Xqcisync' (Qualcomm uC Sync Delay Extension)">;
 
 def FeatureVendorXqci
-    : RISCVExperimentalExtension<0, 13, "Qualcomm uC Extension",
-                                 [FeatureVendorXqcia, FeatureVendorXqciac,
-                                 FeatureVendorXqcibi, FeatureVendorXqcibm,
-...
[truncated]

llvmbot · 2025-12-23T02:58:00Z

@llvm/pr-subscribers-clang-driver

Author: Sudharsan Veeravalli (svs-quic)

Changes

Version 0.13 of the Xqci Qualcomm uC Vendor Extension has been marked as frozen. We've had assembler support for this since LLVM20 and code generation support since LLVM21. I think we have enough coverage in the code base to mark the extension as non-experimental.

Patch is 159.37 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/173331.diff

98 Files Affected:

(modified) clang/test/Driver/print-supported-extensions-riscv.c (+19-19)
(modified) llvm/docs/RISCVUsage.rst (+21-18)
(modified) llvm/docs/ReleaseNotes.md (+1)
(modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+39-42)
(modified) llvm/test/CodeGen/RISCV/attributes-qc.ll (+18-18)
(modified) llvm/test/CodeGen/RISCV/cmov-branch-opt.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/codemodel-lowering.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/features-info.ll (+19-19)
(modified) llvm/test/CodeGen/RISCV/fold-addi-loadstore.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/i32-icmp.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/imm.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/jumptable.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/make-compressible-xqci.mir (+4-4)
(modified) llvm/test/CodeGen/RISCV/min-max.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/pr148084.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/qci-interrupt-attr-fpr.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/qci-interrupt-attr.ll (+6-6)
(modified) llvm/test/CodeGen/RISCV/select-bare.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/select-cc.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/select-cond.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/select-const.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/select.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/short-forward-branch-load-imm.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/short-forward-branch-opt-qcloads.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/stack-offset.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/xqcia.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/xqciac.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/xqcibi.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/xqcibm-cto-clo-brev.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/xqcibm-extract.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/xqcibm-insbi.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/xqcibm-insert.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/xqcicli.ll (+2-2)
(modified) llvm/test/CodeGen/RISCV/xqcicm.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/xqcics.ll (+3-3)
(modified) llvm/test/CodeGen/RISCV/xqcilia.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/xqcilo.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/xqcilsm-lwmi-swmi.mir (+1-1)
(modified) llvm/test/CodeGen/RISCV/xqcilsm-memset.ll (+1-1)
(modified) llvm/test/CodeGen/RISCV/xqcisls.ll (+1-1)
(modified) llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll (+3-3)
(modified) llvm/test/MC/Disassembler/RISCV/branch-targets-xqci.txt (+2-2)
(modified) llvm/test/MC/Disassembler/RISCV/xqci-invalid.txt (+2-2)
(modified) llvm/test/MC/RISCV/insn_xqci.s (+1-1)
(modified) llvm/test/MC/RISCV/rv32-relaxation-xqci.s (+3-3)
(modified) llvm/test/MC/RISCV/vendor-symbol.s (+1-1)
(modified) llvm/test/MC/RISCV/xqci-fixups.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcia-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcia-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqciac-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqciac-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcibi-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcibi-linker-relaxation.s (+1-1)
(modified) llvm/test/MC/RISCV/xqcibi-long-conditional-jump.s (+4-4)
(modified) llvm/test/MC/RISCV/xqcibi-relocations.s (+3-3)
(modified) llvm/test/MC/RISCV/xqcibi-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcibm-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcibm-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcicli-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcicli-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcicm-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcicm-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcics-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcics-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcicsr-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcicsr-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqciint-csrs-invalid.s (+63-63)
(modified) llvm/test/MC/RISCV/xqciint-csrs-valid.s (+3-3)
(modified) llvm/test/MC/RISCV/xqciint-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqciint-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqciio-aliases-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqciio-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqciio-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcilb-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcilb-relocations.s (+3-3)
(modified) llvm/test/MC/RISCV/xqcilb-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcili-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcili-li.s (+1-1)
(modified) llvm/test/MC/RISCV/xqcili-linker-relaxation.s (+1-1)
(modified) llvm/test/MC/RISCV/xqcili-relocations.s (+3-3)
(modified) llvm/test/MC/RISCV/xqcili-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcilia-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcilia-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcilo-aliases-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcilo-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcilo-pseudos-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcilo-pseudos-valid.s (+1-1)
(modified) llvm/test/MC/RISCV/xqcilo-valid.s (+12-12)
(modified) llvm/test/MC/RISCV/xqcilsm-aliases-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcilsm-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcilsm-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcisim-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcisim-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcisls-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcisls-valid.s (+6-6)
(modified) llvm/test/MC/RISCV/xqcisync-invalid.s (+2-2)
(modified) llvm/test/MC/RISCV/xqcisync-valid.s (+6-6)
(modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+19-19)

diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index bcc00d072c2ae..4be310244715e 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -178,6 +178,25 @@
 // CHECK-NEXT:     xmipscmov            1.0       'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov))
 // CHECK-NEXT:     xmipsexectl          1.0       'XMIPSEXECTL' (MIPS execution control)
 // CHECK-NEXT:     xmipslsp             1.0       'XMIPSLSP' (MIPS optimization for hardware load-store bonding)
+// CHECK-NEXT:     xqci                 0.13      'Xqci' (Qualcomm uC Extension)
+// CHECK-NEXT:     xqcia                0.7       'Xqcia' (Qualcomm uC Arithmetic Extension)
+// CHECK-NEXT:     xqciac               0.3       'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)
+// CHECK-NEXT:     xqcibi               0.2       'Xqcibi' (Qualcomm uC Branch Immediate Extension)
+// CHECK-NEXT:     xqcibm               0.8       'Xqcibm' (Qualcomm uC Bit Manipulation Extension)
+// CHECK-NEXT:     xqcicli              0.3       'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)
+// CHECK-NEXT:     xqcicm               0.2       'Xqcicm' (Qualcomm uC Conditional Move Extension)
+// CHECK-NEXT:     xqcics               0.2       'Xqcics' (Qualcomm uC Conditional Select Extension)
+// CHECK-NEXT:     xqcicsr              0.4       'Xqcicsr' (Qualcomm uC CSR Extension)
+// CHECK-NEXT:     xqciint              0.10      'Xqciint' (Qualcomm uC Interrupts Extension)
+// CHECK-NEXT:     xqciio               0.1       'Xqciio' (Qualcomm uC External Input Output Extension)
+// CHECK-NEXT:     xqcilb               0.2       'Xqcilb' (Qualcomm uC Long Branch Extension)
+// CHECK-NEXT:     xqcili               0.2       'Xqcili' (Qualcomm uC Load Large Immediate Extension)
+// CHECK-NEXT:     xqcilia              0.2       'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
+// CHECK-NEXT:     xqcilo               0.3       'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
+// CHECK-NEXT:     xqcilsm              0.6       'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
+// CHECK-NEXT:     xqcisim              0.2       'Xqcisim' (Qualcomm uC Simulation Hint Extension)
+// CHECK-NEXT:     xqcisls              0.2       'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
+// CHECK-NEXT:     xqcisync             0.3       'Xqcisync' (Qualcomm uC Sync Delay Extension)
 // CHECK-NEXT:     xsfcease             1.0       'XSfcease' (SiFive sf.cease Instruction)
 // CHECK-NEXT:     xsfmm128t            0.6       'XSfmm128t' (TE=128 configuration)
 // CHECK-NEXT:     xsfmm16t             0.6       'XSfmm16t' (TE=16 configuration)
@@ -230,25 +249,6 @@
 // CHECK-NEXT:     smpmpmt              0.6       'Smpmpmt' (PMP-based Memory Types Extension)
 // CHECK-NEXT:     svukte               0.3       'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)
 // CHECK-NEXT:     xqccmp               0.3       'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)
-// CHECK-NEXT:     xqci                 0.13      'Xqci' (Qualcomm uC Extension)
-// CHECK-NEXT:     xqcia                0.7       'Xqcia' (Qualcomm uC Arithmetic Extension)
-// CHECK-NEXT:     xqciac               0.3       'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)
-// CHECK-NEXT:     xqcibi               0.2       'Xqcibi' (Qualcomm uC Branch Immediate Extension)
-// CHECK-NEXT:     xqcibm               0.8       'Xqcibm' (Qualcomm uC Bit Manipulation Extension)
-// CHECK-NEXT:     xqcicli              0.3       'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)
-// CHECK-NEXT:     xqcicm               0.2       'Xqcicm' (Qualcomm uC Conditional Move Extension)
-// CHECK-NEXT:     xqcics               0.2       'Xqcics' (Qualcomm uC Conditional Select Extension)
-// CHECK-NEXT:     xqcicsr              0.4       'Xqcicsr' (Qualcomm uC CSR Extension)
-// CHECK-NEXT:     xqciint              0.10      'Xqciint' (Qualcomm uC Interrupts Extension)
-// CHECK-NEXT:     xqciio               0.1       'Xqciio' (Qualcomm uC External Input Output Extension)
-// CHECK-NEXT:     xqcilb               0.2       'Xqcilb' (Qualcomm uC Long Branch Extension)
-// CHECK-NEXT:     xqcili               0.2       'Xqcili' (Qualcomm uC Load Large Immediate Extension)
-// CHECK-NEXT:     xqcilia              0.2       'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)
-// CHECK-NEXT:     xqcilo               0.3       'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)
-// CHECK-NEXT:     xqcilsm              0.6       'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)
-// CHECK-NEXT:     xqcisim              0.2       'Xqcisim' (Qualcomm uC Simulation Hint Extension)
-// CHECK-NEXT:     xqcisls              0.2       'Xqcisls' (Qualcomm uC Scaled Load Store Extension)
-// CHECK-NEXT:     xqcisync             0.3       'Xqcisync' (Qualcomm uC Sync Delay Extension)
 // CHECK-NEXT:     xrivosvisni          0.1       'XRivosVisni' (Rivos Vector Integer Small New)
 // CHECK-NEXT:     xrivosvizip          0.1       'XRivosVizip' (Rivos Vector Register Zips)
 // CHECK-NEXT:     xsfmclic             0.1       'XSfmclic' (SiFive CLIC Machine-mode CSRs)
diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
index 1e55fea9e1eb8..df5a595e8ec93 100644
--- a/llvm/docs/RISCVUsage.rst
+++ b/llvm/docs/RISCVUsage.rst
@@ -463,58 +463,61 @@ The current vendor extensions supported are:
 ``experimental-Xqccmp``
   LLVM implements `version 0.3 of the 16-bit Push/Pop instructions and double-moves extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqccmp_extension-0.3.0>`__ by Qualcomm. All instructions are prefixed with `qc.` as described in the specification.
 
-``experimental-Xqcia``
+``Xqci``
+  LLVM implements `version 0.13 of the Qualcomm uC extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
+
+``Xqcia``
   LLVM implements `version 0.7 of the Qualcomm uC Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqciac``
+``Xqciac``
   LLVM implements `version 0.3 of the Qualcomm uC Load-Store Address Calculation extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcibi``
+``Xqcibi``
   LLVM implements `version 0.2 of the Qualcomm uC Branch Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcibm``
+``Xqcibm``
   LLVM implements `version 0.8 of the Qualcomm uC Bit Manipulation extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcicli``
+``Xqcicli``
   LLVM implements `version 0.3 of the Qualcomm uC Conditional Load Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcicm``
+``Xqcicm``
   LLVM implements `version 0.2 of the Qualcomm uC Conditional Move extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcics``
+``Xqcics``
   LLVM implements `version 0.2 of the Qualcomm uC Conditional Select extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcicsr``
+``Xqcicsr``
   LLVM implements `version 0.4 of the Qualcomm uC CSR extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqciint``
+``Xqciint``
   LLVM implements `version 0.10 of the Qualcomm uC Interrupts extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqciio``
+``Xqciio``
   LLVM implements `version 0.1 of the Qualcomm uC External Input Output extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcilb``
+``Xqcilb``
   LLVM implements `version 0.2 of the Qualcomm uC Long Branch extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcili``
+``Xqcili``
   LLVM implements `version 0.2 of the Qualcomm uC Load Large Immediate extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcilia``
+``Xqcilia``
   LLVM implements `version 0.2 of the Qualcomm uC Large Immediate Arithmetic extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcilo``
+``Xqcilo``
   LLVM implements `version 0.3 of the Qualcomm uC Large Offset Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcilsm``
+``Xqcilsm``
   LLVM implements `version 0.6 of the Qualcomm uC Load Store Multiple extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcisim``
+``Xqcisim``
   LLVM implements `version 0.2 of the Qualcomm uC Simulation Hint extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcisls``
+``Xqcisls``
   LLVM implements `version 0.2 of the Qualcomm uC Scaled Load Store extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
-``experimental-Xqcisync``
+``Xqcisync``
   LLVM implements `version 0.3 of the Qualcomm uC Sync Delay extension specification <https://github.com/quic/riscv-unified-db/releases/tag/Xqci-0.13.0>`__ by Qualcomm. These instructions are only available for riscv32.
 
 ``Xmipscbop``
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 503cf641a221f..910a50214df2f 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -158,6 +158,7 @@ Changes to the RISC-V Backend
 * Adds assembler support for the Andes `XAndesvsinth` (Andes Vector Small Int Handling Extension).
 * DWARF fission is now compatible with linker relaxations, allowing `-gsplit-dwarf` and `-mrelax`
   to be used together when building for the RISC-V platform.
+* The Xqci Qualcomm uC Vendor Extension is no longger marked as experimental.
 
 Changes to the WebAssembly Backend
 ----------------------------------
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 3a76ac6351fdf..66e1b18f37392 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1497,47 +1497,46 @@ def HasVendorXqccmp
                          "'Xqccmp' (Qualcomm 16-bit Push/Pop and Double Moves)">;
 
 def FeatureVendorXqcia
-    : RISCVExperimentalExtension<0, 7, "Qualcomm uC Arithmetic Extension">;
+    : RISCVExtension<0, 7, "Qualcomm uC Arithmetic Extension">;
 def HasVendorXqcia
     : Predicate<"Subtarget->hasVendorXqcia()">,
       AssemblerPredicate<(all_of FeatureVendorXqcia),
                          "'Xqcia' (Qualcomm uC Arithmetic Extension)">;
 
 def FeatureVendorXqciac
-    : RISCVExperimentalExtension<0, 3, "Qualcomm uC Load-Store Address Calculation Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 3, "Qualcomm uC Load-Store Address Calculation Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqciac
     : Predicate<"Subtarget->hasVendorXqciac()">,
       AssemblerPredicate<(all_of FeatureVendorXqciac),
                          "'Xqciac' (Qualcomm uC Load-Store Address Calculation Extension)">;
 
 def FeatureVendorXqcibi
-    : RISCVExperimentalExtension<0, 2, "Qualcomm uC Branch Immediate Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 2, "Qualcomm uC Branch Immediate Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqcibi
     : Predicate<"Subtarget->hasVendorXqcibi()">,
       AssemblerPredicate<(all_of FeatureVendorXqcibi),
                          "'Xqcibi' (Qualcomm uC Branch Immediate Extension)">;
 
 def FeatureVendorXqcibm
-    : RISCVExperimentalExtension<0, 8, "Qualcomm uC Bit Manipulation Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 8, "Qualcomm uC Bit Manipulation Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqcibm
     : Predicate<"Subtarget->hasVendorXqcibm()">,
       AssemblerPredicate<(all_of FeatureVendorXqcibm),
                          "'Xqcibm' (Qualcomm uC Bit Manipulation Extension)">;
 
 def FeatureVendorXqcicli
-    : RISCVExperimentalExtension<0, 3,
-                                 "Qualcomm uC Conditional Load Immediate Extension">;
+    : RISCVExtension<0, 3, "Qualcomm uC Conditional Load Immediate Extension">;
 def HasVendorXqcicli
     : Predicate<"Subtarget->hasVendorXqcicli()">,
       AssemblerPredicate<(all_of FeatureVendorXqcicli),
                          "'Xqcicli' (Qualcomm uC Conditional Load Immediate Extension)">;
 
 def FeatureVendorXqcicm
-    : RISCVExperimentalExtension<0, 2, "Qualcomm uC Conditional Move Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 2, "Qualcomm uC Conditional Move Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqcicm
     : Predicate<"Subtarget->hasVendorXqcicm()">,
       AssemblerPredicate<(all_of FeatureVendorXqcicm),
@@ -1546,7 +1545,7 @@ def NoVendorXqcicm
     : Predicate<"!Subtarget->hasVendorXqcicm()">;
 
 def FeatureVendorXqcics
-    : RISCVExperimentalExtension<0, 2, "Qualcomm uC Conditional Select Extension">;
+    : RISCVExtension<0, 2, "Qualcomm uC Conditional Select Extension">;
 def HasVendorXqcics
     : Predicate<"Subtarget->hasVendorXqcics()">,
       AssemblerPredicate<(all_of FeatureVendorXqcics),
@@ -1555,102 +1554,100 @@ def NoVendorXqcics
     : Predicate<"!Subtarget->hasVendorXqcics()">;
 
 def FeatureVendorXqcicsr
-    : RISCVExperimentalExtension<0, 4, "Qualcomm uC CSR Extension">;
+    : RISCVExtension<0, 4, "Qualcomm uC CSR Extension">;
 def HasVendorXqcicsr
     : Predicate<"Subtarget->hasVendorXqcicsr()">,
       AssemblerPredicate<(all_of FeatureVendorXqcicsr),
                          "'Xqcicsr' (Qualcomm uC CSR Extension)">;
 
 def FeatureVendorXqciint
-    : RISCVExperimentalExtension<0, 10, "Qualcomm uC Interrupts Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 10, "Qualcomm uC Interrupts Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqciint
     : Predicate<"Subtarget->hasVendorXqciint()">,
       AssemblerPredicate<(all_of FeatureVendorXqciint),
                          "'Xqciint' (Qualcomm uC Interrupts Extension)">;
 
 def FeatureVendorXqciio
-    : RISCVExperimentalExtension<0, 1, "Qualcomm uC External Input Output Extension">;
+    : RISCVExtension<0, 1, "Qualcomm uC External Input Output Extension">;
 def HasVendorXqciio
     : Predicate<"Subtarget->hasVendorXqciio()">,
       AssemblerPredicate<(all_of FeatureVendorXqciio),
                          "'Xqciio' (Qualcomm uC External Input Output Extension)">;
 
 def FeatureVendorXqcilb
-    : RISCVExperimentalExtension<0, 2, "Qualcomm uC Long Branch Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 2, "Qualcomm uC Long Branch Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqcilb
     : Predicate<"Subtarget->hasVendorXqcilb()">,
       AssemblerPredicate<(all_of FeatureVendorXqcilb),
                          "'Xqcilb' (Qualcomm uC Long Branch Extension)">;
 
 def FeatureVendorXqcili
-    : RISCVExperimentalExtension<0, 2, "Qualcomm uC Load Large Immediate Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 2, "Qualcomm uC Load Large Immediate Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqcili
     : Predicate<"Subtarget->hasVendorXqcili()">,
       AssemblerPredicate<(all_of FeatureVendorXqcili),
                          "'Xqcili' (Qualcomm uC Load Large Immediate Extension)">;
 
 def FeatureVendorXqcilia
-    : RISCVExperimentalExtension<0, 2, "Qualcomm uC Large Immediate Arithmetic Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 2, "Qualcomm uC Large Immediate Arithmetic Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqcilia
     : Predicate<"Subtarget->hasVendorXqcilia()">,
       AssemblerPredicate<(all_of FeatureVendorXqcilia),
                          "'Xqcilia' (Qualcomm uC Large Immediate Arithmetic Extension)">;
 
 def FeatureVendorXqcilo
-    : RISCVExperimentalExtension<0, 3, "Qualcomm uC Large Offset Load Store Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 3, "Qualcomm uC Large Offset Load Store Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqcilo
     : Predicate<"Subtarget->hasVendorXqcilo()">,
       AssemblerPredicate<(all_of FeatureVendorXqcilo),
                          "'Xqcilo' (Qualcomm uC Large Offset Load Store Extension)">;
 
 def FeatureVendorXqcilsm
-    : RISCVExperimentalExtension<0, 6,
-                                 "Qualcomm uC Load Store Multiple Extension">;
+    : RISCVExtension<0, 6, "Qualcomm uC Load Store Multiple Extension">;
 def HasVendorXqcilsm
     : Predicate<"Subtarget->hasVendorXqcilsm()">,
       AssemblerPredicate<(all_of FeatureVendorXqcilsm),
                          "'Xqcilsm' (Qualcomm uC Load Store Multiple Extension)">;
 
 def FeatureVendorXqcisim
-    : RISCVExperimentalExtension<0, 2, "Qualcomm uC Simulation Hint Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 2, "Qualcomm uC Simulation Hint Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqcisim
     : Predicate<"Subtarget->hasVendorXqcisim()">,
       AssemblerPredicate<(all_of FeatureVendorXqcisim),
                          "'Xqcisim' (Qualcomm uC Simulation Hint Extension)">;
 
 def FeatureVendorXqcisls
-    : RISCVExperimentalExtension<0, 2,
-                                 "Qualcomm uC Scaled Load Store Extension">;
+    : RISCVExtension<0, 2, "Qualcomm uC Scaled Load Store Extension">;
 def HasVendorXqcisls
     : Predicate<"Subtarget->hasVendorXqcisls()">,
       AssemblerPredicate<(all_of FeatureVendorXqcisls),
                          "'Xqcisls' (Qualcomm uC Scaled Load Store Extension)">;
 
 def FeatureVendorXqcisync
-    : RISCVExperimentalExtension<0, 3, "Qualcomm uC Sync Delay Extension",
-                                 [FeatureStdExtZca]>;
+    : RISCVExtension<0, 3, "Qualcomm uC Sync Delay Extension",
+                     [FeatureStdExtZca]>;
 def HasVendorXqcisync
     : Predicate<"Subtarget->hasVendorXqcisync()">,
       AssemblerPredicate<(all_of FeatureVendorXqcisync),
                          "'Xqcisync' (Qualcomm uC Sync Delay Extension)">;
 
 def FeatureVendorXqci
-    : RISCVExperimentalExtension<0, 13, "Qualcomm uC Extension",
-                                 [FeatureVendorXqcia, FeatureVendorXqciac,
-                                 FeatureVendorXqcibi, FeatureVendorXqcibm,
-...
[truncated]

github-actions · 2025-12-23T03:22:16Z

🐧 Linux x64 Test Results

194431 tests passed
6311 tests skipped

✅ The build succeeded and all tests passed.

github-actions · 2025-12-23T03:22:17Z

🪟 Windows x64 Test Results

130392 tests passed
4046 tests skipped

✅ The build succeeded and all tests passed.

Xqci non-experimental

8a4bc5e

llvmbot added backend:RISC-V clang:driver 'clang' and 'clang++' user-facing binaries. Not 'clang-cl' debuginfo labels Dec 23, 2025

svs-quic added 2 commits December 23, 2025 10:11

fix test

0868864

SemaRISCV.cpp change

171cc3e

llvmbot added the clang:frontend Language frontend issues, e.g. anything involving "Sema" label Dec 23, 2025

svs-quic requested review from apazos, hchandel, lenary, pgodeq and topperc December 23, 2025 07:31

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Uh oh!

[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental #173331

[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental #173331

svs-quic commented Dec 23, 2025

Uh oh!

llvmbot commented Dec 23, 2025 •

edited

Loading

Uh oh!

llvmbot commented Dec 23, 2025

Uh oh!

github-actions bot commented Dec 23, 2025 •

edited

Loading

Uh oh!

github-actions bot commented Dec 23, 2025 •

edited

Loading

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

2 participants

[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental #173331

Are you sure you want to change the base?

[RISCV] Mark the Xqci Qualcomm uC Vendor Extension as non-experimental #173331

Conversation

svs-quic commented Dec 23, 2025

Uh oh!

llvmbot commented Dec 23, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

Uh oh!

llvmbot commented Dec 23, 2025

Uh oh!

github-actions bot commented Dec 23, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

🐧 Linux x64 Test Results

Uh oh!

github-actions bot commented Dec 23, 2025 • edited Loading Uh oh! There was an error while loading. Please reload this page.

Uh oh!

🪟 Windows x64 Test Results

Uh oh!

Reviewers

Assignees

Labels

Projects

Milestone

Development

Uh oh!

2 participants

llvmbot commented Dec 23, 2025 •

edited

Loading

github-actions bot commented Dec 23, 2025 •

edited

Loading

github-actions bot commented Dec 23, 2025 •

edited

Loading