[X86][SelectionDAG] Register type affect DAG ISel#179446
[X86][SelectionDAG] Register type affect DAG ISel#179446
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@llvm/pr-subscribers-llvm-selectiondag Author: woruyu (woruyu) ChangesSummaryThis PR resolves #179100, the related PR: #164565 Full diff: https://github.com/llvm/llvm-project/pull/179446.diff 1 Files Affected:
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 63c9d193421ea..ea3192208a81e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -2017,13 +2017,8 @@ SDValue SelectionDAGBuilder::getValueImpl(const Value *V) {
if (const Instruction *Inst = dyn_cast<Instruction>(V)) {
Register InReg = FuncInfo.InitializeRegForValue(Inst);
- std::optional<CallingConv::ID> CallConv;
- auto *CB = dyn_cast<CallBase>(Inst);
- if (CB && !CB->isInlineAsm())
- CallConv = CB->getCallingConv();
-
RegsForValue RFV(*DAG.getContext(), TLI, DAG.getDataLayout(), InReg,
- Inst->getType(), CallConv);
+ Inst->getType(), std::nullopt);
SDValue Chain = DAG.getEntryNode();
return RFV.getCopyFromRegs(DAG, FuncInfo, getCurSDLoc(), Chain, nullptr, V);
}
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// Old DAG
SelectionDAG has 25 nodes:
t0: ch,glue = EntryToken
t3: v4i1 = BUILD_VECTOR Constant:i1<0>, Constant:i1<0>, Constant:i1<0>, Constant:i1<0>
t10: ch,glue = callseq_start t0, TargetConstant:i64<0>, TargetConstant:i64<0>
t12: ch,glue = CopyToReg t10, Register:i64 $rdi, Constant:i64<0>
t7: v4i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<0>, Constant:i32<0>, Constant:i32<0>
t14: ch,glue = CopyToReg t12, Register:v4i32 $xmm0, t7, t12:1
t5: v4i1,ch = CopyFromReg t0, Register:v4i1 %3
t8: v4i32 = any_extend t5
t16: ch,glue = CopyToReg t14, Register:v4i32 $xmm1, t8, t14:1
t18: ch,glue = X86ISD::CALL t16, Constant:i64<0>, Register:i64 $rdi, Register:v4i32 $xmm0, Register:v4i32 $xmm1, RegisterMask:Untyped, t16:1
t19: ch,glue = callseq_end t18, TargetConstant:i64<0>, TargetConstant:i64<0>, t18:1
t21: i16,ch,glue = CopyFromReg t19, Register:i16 $ax, t19:1
t23: ch = CopyToReg t0, Register:i16 %0, t21
t24: ch = TokenFactor t23, t21:1
// Cur DAG
SelectionDAG has 25 nodes:
t0: ch,glue = EntryToken
t3: v4i1 = BUILD_VECTOR Constant:i1<0>, Constant:i1<0>, Constant:i1<0>, Constant:i1<0>
t5: v4i32,ch = CopyFromReg t0, Register:v4i32 %3
t6: v4i1 = truncate t5
t10: ch,glue = callseq_start t0, TargetConstant:i64<0>, TargetConstant:i64<0>
t12: ch,glue = CopyToReg t10, Register:i64 $rdi, Constant:i64<0>
t8: v4i32 = BUILD_VECTOR Constant:i32<0>, Constant:i32<0>, Constant:i32<0>, Constant:i32<0>
t14: ch,glue = CopyToReg t12, Register:v4i32 $xmm0, t8, t12:1
t16: ch,glue = CopyToReg t14, Register:v4i32 $xmm1, t5, t14:1
t18: ch,glue = X86ISD::CALL t16, Constant:i64<0>, Register:i64 $rdi, Register:v4i32 $xmm0, Register:v4i32 $xmm1, RegisterMask:Untyped, t16:1
t19: ch,glue = callseq_end t18, TargetConstant:i64<0>, TargetConstant:i64<0>, t18:1
t21: i16,ch,glue = CopyFromReg t19, Register:i16 $ax, t19:1
t23: ch = CopyToReg t0, Register:i16 %0, t21
t24: ch = TokenFactor t23, t21:1The difference comes from the virtual register type. In the old DAG, the value is carried as v4i1, which matches the source-level semantics. In the new DAG it is carried as v4i32. As a result, the new lowering no longer produces the explicit step: t8: v4i32 = any_extend t5 However, that any_extend is not “free”: it still has to be legalized/selected later, typically into something like: t25: v4i32 = VPMOVM2DZ128rk t5 I understand the overall pipeline, but I’m not sure what the best approach is to avoid or handle this missing any_extend step. Any suggestions? |
understand, but I don't come up with a suitable method to fix both |
🐧 Linux x64 Test Results
Failed Tests(click on a test name to see its output) LLVMLLVM.CodeGen/X86/bf16-fast-isel.llIf these failures are unrelated to your changes (for example tests are broken or flaky at HEAD), please open an issue at https://github.com/llvm/llvm-project/issues and add the |
🪟 Windows x64 Test Results
Failed Tests(click on a test name to see its output) LLVMLLVM.CodeGen/X86/bf16-fast-isel.llIf these failures are unrelated to your changes (for example tests are broken or flaky at HEAD), please open an issue at https://github.com/llvm/llvm-project/issues and add the |
I'm not too worried about this situation -- I'm sure #179100 will be resolved one way or another in time for the 21.1.0 tag -- but just as a point of order, I think it's worth noting that per the developer policy, it is actually the responsibility of a committer to resolve any regressions caused by a commit - ideally with a follow-up fix, but failing that, a revert. Barring exceptional circumstances (probably requiring an RFC), we can't get into a situation where we justify breaking existing valid code to fix some other code; that approach will quickly break down in a project the scale of LLVM. |
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I got a rough patch #180322 to fix this issue. I need more time to know the fastISel behavior. |
Summary
This PR resolves #179100, the related PR: #164565