release/22.x: [Hexagon] Define __HVX_IEEE_FP__ ; Use __HVX_IEEE_FP__ to guard protos by androm3da · Pull Request #185014 · llvm/llvm-project

androm3da · 2026-03-06T14:47:47Z

No description provided.

…183829) Add a __HVX_IEEE_FP__ define when the compiler is invoked with -mhvx-ieee-fp flag

…llvm#184422) Hexagon clang recently started to define __HVX_IEEE_FP__ when the -mhvx-ieee-fp option is specified. Guard the intrinsic macros for instructions that should only be available with -mhvx-ieee-fp with __HVX_IEEE_FP__. Additionally, the following NFC changes are included: - NFC: Remove guards around HVX v60 intrinsic macros Hexagon v60 is the oldest Hexagon version that supports HVX so these guards were redundant. Presence of HVX is guarded separately, once per the whole file. - Remove comments from closing guards (HVX protos) These comments served very limited function as they only guard one macro. Also, they were incorrect. Instead of fixing remove them. This will also reduce by the factor of two the amount of changes when guarding conditions change.

llvmbot · 2026-03-06T14:48:22Z

@llvm/pr-subscribers-clang

Author: Brian Cain (androm3da)

Changes

Patch is 247.93 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/185014.diff

5 Files Affected:

(modified) clang/lib/Basic/Targets/Hexagon.cpp (+6)
(modified) clang/lib/Basic/Targets/Hexagon.h (+1)
(modified) clang/lib/Headers/hvx_hexagon_protos.h (+287-891)
(added) clang/test/Headers/hexagon-hvx-ieee-headers.c (+20)
(modified) clang/test/Preprocessor/hexagon-predefines.c (+13)

diff --git a/clang/lib/Basic/Targets/Hexagon.cpp b/clang/lib/Basic/Targets/Hexagon.cpp
index bd70bfe4fef51..9bf34e67a03fd 100644
--- a/clang/lib/Basic/Targets/Hexagon.cpp
+++ b/clang/lib/Basic/Targets/Hexagon.cpp
@@ -102,6 +102,9 @@ void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
       Builder.defineMacro("__HVXDBL__");
   }
 
+  if (HasHVXIeeeFp)
+    Builder.defineMacro("__HVX_IEEE_FP__");
+
   if (hasFeature("audio")) {
     Builder.defineMacro("__HEXAGON_AUDIO__");
   }
@@ -148,6 +151,8 @@ bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
       UseLongCalls = true;
     else if (F == "-long-calls")
       UseLongCalls = false;
+    else if (F == "+hvx-ieee-fp")
+      HasHVXIeeeFp = true;
     else if (F == "+audio")
       HasAudio = true;
   }
@@ -242,6 +247,7 @@ bool HexagonTargetInfo::hasFeature(StringRef Feature) const {
       .Case("hvx", HasHVX)
       .Case("hvx-length64b", HasHVX64B)
       .Case("hvx-length128b", HasHVX128B)
+      .Case("hvx-ieee-fp", HasHVXIeeeFp)
       .Case("long-calls", UseLongCalls)
       .Case("audio", HasAudio)
       .Default(false);
diff --git a/clang/lib/Basic/Targets/Hexagon.h b/clang/lib/Basic/Targets/Hexagon.h
index 21da0fc4cbdd0..f034911d77b92 100644
--- a/clang/lib/Basic/Targets/Hexagon.h
+++ b/clang/lib/Basic/Targets/Hexagon.h
@@ -32,6 +32,7 @@ class LLVM_LIBRARY_VISIBILITY HexagonTargetInfo : public TargetInfo {
   bool HasHVX = false;
   bool HasHVX64B = false;
   bool HasHVX128B = false;
+  bool HasHVXIeeeFp = false;
   bool HasAudio = false;
   bool UseLongCalls = false;
 
diff --git a/clang/lib/Headers/hvx_hexagon_protos.h b/clang/lib/Headers/hvx_hexagon_protos.h
index 19309a40d6dd1..981fbd1a12f7e 100644
--- a/clang/lib/Headers/hvx_hexagon_protos.h
+++ b/clang/lib/Headers/hvx_hexagon_protos.h
@@ -19,7 +19,6 @@
 #define __BUILTIN_VECTOR_WRAP(a) a
 #endif
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Rd32=vextract(Vu32,Rs32)
    C Intrinsic Prototype: Word32 Q6_R_vextract_VR(HVX_Vector Vu, Word32 Rs)
@@ -28,9 +27,7 @@
    ========================================================================== */
 
 #define Q6_R_vextract_VR(Vu,Rs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_extractw)(Vu,Rs)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32=hi(Vss32)
    C Intrinsic Prototype: HVX_Vector Q6_V_hi_W(HVX_VectorPair Vss)
@@ -39,9 +36,7 @@
    ========================================================================== */
 
 #define Q6_V_hi_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_hi)(Vss)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32=lo(Vss32)
    C Intrinsic Prototype: HVX_Vector Q6_V_lo_W(HVX_VectorPair Vss)
@@ -50,9 +45,7 @@
    ========================================================================== */
 
 #define Q6_V_lo_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lo)(Vss)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32=vsplat(Rt32)
    C Intrinsic Prototype: HVX_Vector Q6_V_vsplat_R(Word32 Rt)
@@ -61,9 +54,7 @@
    ========================================================================== */
 
 #define Q6_V_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw)(Rt)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=and(Qs4,Qt4)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)
@@ -72,9 +63,7 @@
    ========================================================================== */
 
 #define Q6_Q_and_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=and(Qs4,!Qt4)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt)
@@ -83,9 +72,7 @@
    ========================================================================== */
 
 #define Q6_Q_and_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=not(Qs4)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_not_Q(HVX_VectorPred Qs)
@@ -94,9 +81,7 @@
    ========================================================================== */
 
 #define Q6_Q_not_Q(Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_not)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1))),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=or(Qs4,Qt4)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)
@@ -105,9 +90,7 @@
    ========================================================================== */
 
 #define Q6_Q_or_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=or(Qs4,!Qt4)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt)
@@ -116,9 +99,7 @@
    ========================================================================== */
 
 #define Q6_Q_or_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=vsetq(Rt32)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq_R(Word32 Rt)
@@ -127,9 +108,7 @@
    ========================================================================== */
 
 #define Q6_Q_vsetq_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2)(Rt)),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=xor(Qs4,Qt4)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_xor_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)
@@ -138,9 +117,7 @@
    ========================================================================== */
 
 #define Q6_Q_xor_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (!Qv4) vmem(Rt32+#s4)=Vs32
    C Intrinsic Prototype: void Q6_vmem_QnRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
@@ -149,9 +126,7 @@
    ========================================================================== */
 
 #define Q6_vmem_QnRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (!Qv4) vmem(Rt32+#s4):nt=Vs32
    C Intrinsic Prototype: void Q6_vmem_QnRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
@@ -160,9 +135,7 @@
    ========================================================================== */
 
 #define Q6_vmem_QnRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (Qv4) vmem(Rt32+#s4):nt=Vs32
    C Intrinsic Prototype: void Q6_vmem_QRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
@@ -171,9 +144,7 @@
    ========================================================================== */
 
 #define Q6_vmem_QRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (Qv4) vmem(Rt32+#s4)=Vs32
    C Intrinsic Prototype: void Q6_vmem_QRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
@@ -182,9 +153,7 @@
    ========================================================================== */
 
 #define Q6_vmem_QRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.uh=vabsdiff(Vu32.h,Vv32.h)
    C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VhVh(HVX_Vector Vu, HVX_Vector Vv)
@@ -193,9 +162,7 @@
    ========================================================================== */
 
 #define Q6_Vuh_vabsdiff_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffh)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub)
    C Intrinsic Prototype: HVX_Vector Q6_Vub_vabsdiff_VubVub(HVX_Vector Vu, HVX_Vector Vv)
@@ -204,9 +171,7 @@
    ========================================================================== */
 
 #define Q6_Vub_vabsdiff_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffub)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh)
    C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
@@ -215,9 +180,7 @@
    ========================================================================== */
 
 #define Q6_Vuh_vabsdiff_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffuh)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.uw=vabsdiff(Vu32.w,Vv32.w)
    C Intrinsic Prototype: HVX_Vector Q6_Vuw_vabsdiff_VwVw(HVX_Vector Vu, HVX_Vector Vv)
@@ -226,9 +189,7 @@
    ========================================================================== */
 
 #define Q6_Vuw_vabsdiff_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffw)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.h=vabs(Vu32.h)
    C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh(HVX_Vector Vu)
@@ -237,9 +198,7 @@
    ========================================================================== */
 
 #define Q6_Vh_vabs_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh)(Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.h=vabs(Vu32.h):sat
    C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh_sat(HVX_Vector Vu)
@@ -248,9 +207,7 @@
    ========================================================================== */
 
 #define Q6_Vh_vabs_Vh_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh_sat)(Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.w=vabs(Vu32.w)
    C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw(HVX_Vector Vu)
@@ -259,9 +216,7 @@
    ========================================================================== */
 
 #define Q6_Vw_vabs_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw)(Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.w=vabs(Vu32.w):sat
    C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw_sat(HVX_Vector Vu)
@@ -270,9 +225,7 @@
    ========================================================================== */
 
 #define Q6_Vw_vabs_Vw_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw_sat)(Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.b=vadd(Vu32.b,Vv32.b)
    C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb(HVX_Vector Vu, HVX_Vector Vv)
@@ -281,9 +234,7 @@
    ========================================================================== */
 
 #define Q6_Vb_vadd_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vdd32.b=vadd(Vuu32.b,Vvv32.b)
    C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
@@ -292,9 +243,7 @@
    ========================================================================== */
 
 #define Q6_Wb_vadd_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb_dv)(Vuu,Vvv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (!Qv4) Vx32.b+=Vu32.b
    C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
@@ -303,9 +252,7 @@
    ========================================================================== */
 
 #define Q6_Vb_condacc_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (Qv4) Vx32.b+=Vu32.b
    C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
@@ -314,9 +261,7 @@
    ========================================================================== */
 
 #define Q6_Vb_condacc_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.h=vadd(Vu32.h,Vv32.h)
    C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv)
@@ -325,9 +270,7 @@
    ========================================================================== */
 
 #define Q6_Vh_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vdd32.h=vadd(Vuu32.h,Vvv32.h)
    C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
@@ -336,9 +279,7 @@
    ========================================================================== */
 
 #define Q6_Wh_vadd_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh_dv)(Vuu,Vvv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (!Qv4) Vx32.h+=Vu32.h
    C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
@@ -347,9 +288,7 @@
    ========================================================================== */
 
 #define Q6_Vh_condacc_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (Qv4) Vx32.h+=Vu32.h
    C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
@@ -358,9 +297,7 @@
    ========================================================================== */
 
 #define Q6_Vh_condacc_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.h=vadd(Vu32.h,Vv32.h):sat
    C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
@@ -369,9 +306,7 @@
    ========================================================================== */
 
 #define Q6_Vh_vadd_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat
    C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
@@ -380,9 +315,7 @@
    ========================================================================== */
 
 #define Q6_Wh_vadd_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat_dv)(Vuu,Vvv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vdd32.w=vadd(Vu32.h,Vv32.h)
    C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv)
@@ -391,9 +324,7 @@
    ========================================================================== */
 
 #define Q6_Ww_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vdd32.h=vadd(Vu32.ub,Vv32.ub)
    C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_VubVub(HVX_Vector Vu, HVX_Vector Vv)
@@ -402,9 +333,7 @@
    ========================================================================== */
 
 #define Q6_Wh_vadd_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat
    C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv)
@@ -413,9 +342,7 @@
    ===============================================...
[truncated]

llvmbot · 2026-03-06T14:48:23Z

@llvm/pr-subscribers-backend-x86

Author: Brian Cain (androm3da)

Changes

Patch is 247.93 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/185014.diff

5 Files Affected:

(modified) clang/lib/Basic/Targets/Hexagon.cpp (+6)
(modified) clang/lib/Basic/Targets/Hexagon.h (+1)
(modified) clang/lib/Headers/hvx_hexagon_protos.h (+287-891)
(added) clang/test/Headers/hexagon-hvx-ieee-headers.c (+20)
(modified) clang/test/Preprocessor/hexagon-predefines.c (+13)

diff --git a/clang/lib/Basic/Targets/Hexagon.cpp b/clang/lib/Basic/Targets/Hexagon.cpp
index bd70bfe4fef51..9bf34e67a03fd 100644
--- a/clang/lib/Basic/Targets/Hexagon.cpp
+++ b/clang/lib/Basic/Targets/Hexagon.cpp
@@ -102,6 +102,9 @@ void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
       Builder.defineMacro("__HVXDBL__");
   }
 
+  if (HasHVXIeeeFp)
+    Builder.defineMacro("__HVX_IEEE_FP__");
+
   if (hasFeature("audio")) {
     Builder.defineMacro("__HEXAGON_AUDIO__");
   }
@@ -148,6 +151,8 @@ bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
       UseLongCalls = true;
     else if (F == "-long-calls")
       UseLongCalls = false;
+    else if (F == "+hvx-ieee-fp")
+      HasHVXIeeeFp = true;
     else if (F == "+audio")
       HasAudio = true;
   }
@@ -242,6 +247,7 @@ bool HexagonTargetInfo::hasFeature(StringRef Feature) const {
       .Case("hvx", HasHVX)
       .Case("hvx-length64b", HasHVX64B)
       .Case("hvx-length128b", HasHVX128B)
+      .Case("hvx-ieee-fp", HasHVXIeeeFp)
       .Case("long-calls", UseLongCalls)
       .Case("audio", HasAudio)
       .Default(false);
diff --git a/clang/lib/Basic/Targets/Hexagon.h b/clang/lib/Basic/Targets/Hexagon.h
index 21da0fc4cbdd0..f034911d77b92 100644
--- a/clang/lib/Basic/Targets/Hexagon.h
+++ b/clang/lib/Basic/Targets/Hexagon.h
@@ -32,6 +32,7 @@ class LLVM_LIBRARY_VISIBILITY HexagonTargetInfo : public TargetInfo {
   bool HasHVX = false;
   bool HasHVX64B = false;
   bool HasHVX128B = false;
+  bool HasHVXIeeeFp = false;
   bool HasAudio = false;
   bool UseLongCalls = false;
 
diff --git a/clang/lib/Headers/hvx_hexagon_protos.h b/clang/lib/Headers/hvx_hexagon_protos.h
index 19309a40d6dd1..981fbd1a12f7e 100644
--- a/clang/lib/Headers/hvx_hexagon_protos.h
+++ b/clang/lib/Headers/hvx_hexagon_protos.h
@@ -19,7 +19,6 @@
 #define __BUILTIN_VECTOR_WRAP(a) a
 #endif
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Rd32=vextract(Vu32,Rs32)
    C Intrinsic Prototype: Word32 Q6_R_vextract_VR(HVX_Vector Vu, Word32 Rs)
@@ -28,9 +27,7 @@
    ========================================================================== */
 
 #define Q6_R_vextract_VR(Vu,Rs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_extractw)(Vu,Rs)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32=hi(Vss32)
    C Intrinsic Prototype: HVX_Vector Q6_V_hi_W(HVX_VectorPair Vss)
@@ -39,9 +36,7 @@
    ========================================================================== */
 
 #define Q6_V_hi_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_hi)(Vss)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32=lo(Vss32)
    C Intrinsic Prototype: HVX_Vector Q6_V_lo_W(HVX_VectorPair Vss)
@@ -50,9 +45,7 @@
    ========================================================================== */
 
 #define Q6_V_lo_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lo)(Vss)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32=vsplat(Rt32)
    C Intrinsic Prototype: HVX_Vector Q6_V_vsplat_R(Word32 Rt)
@@ -61,9 +54,7 @@
    ========================================================================== */
 
 #define Q6_V_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw)(Rt)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=and(Qs4,Qt4)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)
@@ -72,9 +63,7 @@
    ========================================================================== */
 
 #define Q6_Q_and_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=and(Qs4,!Qt4)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt)
@@ -83,9 +72,7 @@
    ========================================================================== */
 
 #define Q6_Q_and_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=not(Qs4)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_not_Q(HVX_VectorPred Qs)
@@ -94,9 +81,7 @@
    ========================================================================== */
 
 #define Q6_Q_not_Q(Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_not)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1))),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=or(Qs4,Qt4)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)
@@ -105,9 +90,7 @@
    ========================================================================== */
 
 #define Q6_Q_or_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=or(Qs4,!Qt4)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt)
@@ -116,9 +99,7 @@
    ========================================================================== */
 
 #define Q6_Q_or_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=vsetq(Rt32)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq_R(Word32 Rt)
@@ -127,9 +108,7 @@
    ========================================================================== */
 
 #define Q6_Q_vsetq_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2)(Rt)),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=xor(Qs4,Qt4)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_xor_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)
@@ -138,9 +117,7 @@
    ========================================================================== */
 
 #define Q6_Q_xor_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (!Qv4) vmem(Rt32+#s4)=Vs32
    C Intrinsic Prototype: void Q6_vmem_QnRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
@@ -149,9 +126,7 @@
    ========================================================================== */
 
 #define Q6_vmem_QnRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (!Qv4) vmem(Rt32+#s4):nt=Vs32
    C Intrinsic Prototype: void Q6_vmem_QnRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
@@ -160,9 +135,7 @@
    ========================================================================== */
 
 #define Q6_vmem_QnRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (Qv4) vmem(Rt32+#s4):nt=Vs32
    C Intrinsic Prototype: void Q6_vmem_QRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
@@ -171,9 +144,7 @@
    ========================================================================== */
 
 #define Q6_vmem_QRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (Qv4) vmem(Rt32+#s4)=Vs32
    C Intrinsic Prototype: void Q6_vmem_QRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
@@ -182,9 +153,7 @@
    ========================================================================== */
 
 #define Q6_vmem_QRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.uh=vabsdiff(Vu32.h,Vv32.h)
    C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VhVh(HVX_Vector Vu, HVX_Vector Vv)
@@ -193,9 +162,7 @@
    ========================================================================== */
 
 #define Q6_Vuh_vabsdiff_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffh)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub)
    C Intrinsic Prototype: HVX_Vector Q6_Vub_vabsdiff_VubVub(HVX_Vector Vu, HVX_Vector Vv)
@@ -204,9 +171,7 @@
    ========================================================================== */
 
 #define Q6_Vub_vabsdiff_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffub)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh)
    C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
@@ -215,9 +180,7 @@
    ========================================================================== */
 
 #define Q6_Vuh_vabsdiff_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffuh)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.uw=vabsdiff(Vu32.w,Vv32.w)
    C Intrinsic Prototype: HVX_Vector Q6_Vuw_vabsdiff_VwVw(HVX_Vector Vu, HVX_Vector Vv)
@@ -226,9 +189,7 @@
    ========================================================================== */
 
 #define Q6_Vuw_vabsdiff_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffw)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.h=vabs(Vu32.h)
    C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh(HVX_Vector Vu)
@@ -237,9 +198,7 @@
    ========================================================================== */
 
 #define Q6_Vh_vabs_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh)(Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.h=vabs(Vu32.h):sat
    C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh_sat(HVX_Vector Vu)
@@ -248,9 +207,7 @@
    ========================================================================== */
 
 #define Q6_Vh_vabs_Vh_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh_sat)(Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.w=vabs(Vu32.w)
    C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw(HVX_Vector Vu)
@@ -259,9 +216,7 @@
    ========================================================================== */
 
 #define Q6_Vw_vabs_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw)(Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.w=vabs(Vu32.w):sat
    C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw_sat(HVX_Vector Vu)
@@ -270,9 +225,7 @@
    ========================================================================== */
 
 #define Q6_Vw_vabs_Vw_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw_sat)(Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.b=vadd(Vu32.b,Vv32.b)
    C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb(HVX_Vector Vu, HVX_Vector Vv)
@@ -281,9 +234,7 @@
    ========================================================================== */
 
 #define Q6_Vb_vadd_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vdd32.b=vadd(Vuu32.b,Vvv32.b)
    C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
@@ -292,9 +243,7 @@
    ========================================================================== */
 
 #define Q6_Wb_vadd_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb_dv)(Vuu,Vvv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (!Qv4) Vx32.b+=Vu32.b
    C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
@@ -303,9 +252,7 @@
    ========================================================================== */
 
 #define Q6_Vb_condacc_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (Qv4) Vx32.b+=Vu32.b
    C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
@@ -314,9 +261,7 @@
    ========================================================================== */
 
 #define Q6_Vb_condacc_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.h=vadd(Vu32.h,Vv32.h)
    C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv)
@@ -325,9 +270,7 @@
    ========================================================================== */
 
 #define Q6_Vh_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vdd32.h=vadd(Vuu32.h,Vvv32.h)
    C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
@@ -336,9 +279,7 @@
    ========================================================================== */
 
 #define Q6_Wh_vadd_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh_dv)(Vuu,Vvv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (!Qv4) Vx32.h+=Vu32.h
    C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
@@ -347,9 +288,7 @@
    ========================================================================== */
 
 #define Q6_Vh_condacc_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (Qv4) Vx32.h+=Vu32.h
    C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
@@ -358,9 +297,7 @@
    ========================================================================== */
 
 #define Q6_Vh_condacc_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.h=vadd(Vu32.h,Vv32.h):sat
    C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
@@ -369,9 +306,7 @@
    ========================================================================== */
 
 #define Q6_Vh_vadd_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat
    C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
@@ -380,9 +315,7 @@
    ========================================================================== */
 
 #define Q6_Wh_vadd_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat_dv)(Vuu,Vvv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vdd32.w=vadd(Vu32.h,Vv32.h)
    C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv)
@@ -391,9 +324,7 @@
    ========================================================================== */
 
 #define Q6_Ww_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vdd32.h=vadd(Vu32.ub,Vv32.ub)
    C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_VubVub(HVX_Vector Vu, HVX_Vector Vv)
@@ -402,9 +333,7 @@
    ========================================================================== */
 
 #define Q6_Wh_vadd_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat
    C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv)
@@ -413,9 +342,7 @@
    ===============================================...
[truncated]

llvmbot · 2026-03-06T14:48:23Z

@llvm/pr-subscribers-backend-hexagon

Author: Brian Cain (androm3da)

Changes

Patch is 247.93 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/185014.diff

5 Files Affected:

(modified) clang/lib/Basic/Targets/Hexagon.cpp (+6)
(modified) clang/lib/Basic/Targets/Hexagon.h (+1)
(modified) clang/lib/Headers/hvx_hexagon_protos.h (+287-891)
(added) clang/test/Headers/hexagon-hvx-ieee-headers.c (+20)
(modified) clang/test/Preprocessor/hexagon-predefines.c (+13)

diff --git a/clang/lib/Basic/Targets/Hexagon.cpp b/clang/lib/Basic/Targets/Hexagon.cpp
index bd70bfe4fef51..9bf34e67a03fd 100644
--- a/clang/lib/Basic/Targets/Hexagon.cpp
+++ b/clang/lib/Basic/Targets/Hexagon.cpp
@@ -102,6 +102,9 @@ void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts,
       Builder.defineMacro("__HVXDBL__");
   }
 
+  if (HasHVXIeeeFp)
+    Builder.defineMacro("__HVX_IEEE_FP__");
+
   if (hasFeature("audio")) {
     Builder.defineMacro("__HEXAGON_AUDIO__");
   }
@@ -148,6 +151,8 @@ bool HexagonTargetInfo::handleTargetFeatures(std::vector<std::string> &Features,
       UseLongCalls = true;
     else if (F == "-long-calls")
       UseLongCalls = false;
+    else if (F == "+hvx-ieee-fp")
+      HasHVXIeeeFp = true;
     else if (F == "+audio")
       HasAudio = true;
   }
@@ -242,6 +247,7 @@ bool HexagonTargetInfo::hasFeature(StringRef Feature) const {
       .Case("hvx", HasHVX)
       .Case("hvx-length64b", HasHVX64B)
       .Case("hvx-length128b", HasHVX128B)
+      .Case("hvx-ieee-fp", HasHVXIeeeFp)
       .Case("long-calls", UseLongCalls)
       .Case("audio", HasAudio)
       .Default(false);
diff --git a/clang/lib/Basic/Targets/Hexagon.h b/clang/lib/Basic/Targets/Hexagon.h
index 21da0fc4cbdd0..f034911d77b92 100644
--- a/clang/lib/Basic/Targets/Hexagon.h
+++ b/clang/lib/Basic/Targets/Hexagon.h
@@ -32,6 +32,7 @@ class LLVM_LIBRARY_VISIBILITY HexagonTargetInfo : public TargetInfo {
   bool HasHVX = false;
   bool HasHVX64B = false;
   bool HasHVX128B = false;
+  bool HasHVXIeeeFp = false;
   bool HasAudio = false;
   bool UseLongCalls = false;
 
diff --git a/clang/lib/Headers/hvx_hexagon_protos.h b/clang/lib/Headers/hvx_hexagon_protos.h
index 19309a40d6dd1..981fbd1a12f7e 100644
--- a/clang/lib/Headers/hvx_hexagon_protos.h
+++ b/clang/lib/Headers/hvx_hexagon_protos.h
@@ -19,7 +19,6 @@
 #define __BUILTIN_VECTOR_WRAP(a) a
 #endif
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Rd32=vextract(Vu32,Rs32)
    C Intrinsic Prototype: Word32 Q6_R_vextract_VR(HVX_Vector Vu, Word32 Rs)
@@ -28,9 +27,7 @@
    ========================================================================== */
 
 #define Q6_R_vextract_VR(Vu,Rs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_extractw)(Vu,Rs)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32=hi(Vss32)
    C Intrinsic Prototype: HVX_Vector Q6_V_hi_W(HVX_VectorPair Vss)
@@ -39,9 +36,7 @@
    ========================================================================== */
 
 #define Q6_V_hi_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_hi)(Vss)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32=lo(Vss32)
    C Intrinsic Prototype: HVX_Vector Q6_V_lo_W(HVX_VectorPair Vss)
@@ -50,9 +45,7 @@
    ========================================================================== */
 
 #define Q6_V_lo_W(Vss) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lo)(Vss)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32=vsplat(Rt32)
    C Intrinsic Prototype: HVX_Vector Q6_V_vsplat_R(Word32 Rt)
@@ -61,9 +54,7 @@
    ========================================================================== */
 
 #define Q6_V_vsplat_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_lvsplatw)(Rt)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=and(Qs4,Qt4)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)
@@ -72,9 +63,7 @@
    ========================================================================== */
 
 #define Q6_Q_and_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=and(Qs4,!Qt4)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_and_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt)
@@ -83,9 +72,7 @@
    ========================================================================== */
 
 #define Q6_Q_and_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_and_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=not(Qs4)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_not_Q(HVX_VectorPred Qs)
@@ -94,9 +81,7 @@
    ========================================================================== */
 
 #define Q6_Q_not_Q(Qs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_not)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1))),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=or(Qs4,Qt4)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)
@@ -105,9 +90,7 @@
    ========================================================================== */
 
 #define Q6_Q_or_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=or(Qs4,!Qt4)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_or_QQn(HVX_VectorPred Qs, HVX_VectorPred Qt)
@@ -116,9 +99,7 @@
    ========================================================================== */
 
 #define Q6_Q_or_QQn(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_or_n)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=vsetq(Rt32)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_vsetq_R(Word32 Rt)
@@ -127,9 +108,7 @@
    ========================================================================== */
 
 #define Q6_Q_vsetq_R(Rt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_scalar2)(Rt)),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Qd4=xor(Qs4,Qt4)
    C Intrinsic Prototype: HVX_VectorPred Q6_Q_xor_QQ(HVX_VectorPred Qs, HVX_VectorPred Qt)
@@ -138,9 +117,7 @@
    ========================================================================== */
 
 #define Q6_Q_xor_QQ(Qs,Qt) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandqrt)((__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_pred_xor)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qs),-1),__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qt),-1))),-1)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (!Qv4) vmem(Rt32+#s4)=Vs32
    C Intrinsic Prototype: void Q6_vmem_QnRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
@@ -149,9 +126,7 @@
    ========================================================================== */
 
 #define Q6_vmem_QnRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (!Qv4) vmem(Rt32+#s4):nt=Vs32
    C Intrinsic Prototype: void Q6_vmem_QnRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
@@ -160,9 +135,7 @@
    ========================================================================== */
 
 #define Q6_vmem_QnRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_nqpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (Qv4) vmem(Rt32+#s4):nt=Vs32
    C Intrinsic Prototype: void Q6_vmem_QRIV_nt(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
@@ -171,9 +144,7 @@
    ========================================================================== */
 
 #define Q6_vmem_QRIV_nt(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_nt_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (Qv4) vmem(Rt32+#s4)=Vs32
    C Intrinsic Prototype: void Q6_vmem_QRIV(HVX_VectorPred Qv, HVX_Vector* Rt, HVX_Vector Vs)
@@ -182,9 +153,7 @@
    ========================================================================== */
 
 #define Q6_vmem_QRIV(Qv,Rt,Vs) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vS32b_qpred_ai)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Rt,Vs)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.uh=vabsdiff(Vu32.h,Vv32.h)
    C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VhVh(HVX_Vector Vu, HVX_Vector Vv)
@@ -193,9 +162,7 @@
    ========================================================================== */
 
 #define Q6_Vuh_vabsdiff_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffh)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.ub=vabsdiff(Vu32.ub,Vv32.ub)
    C Intrinsic Prototype: HVX_Vector Q6_Vub_vabsdiff_VubVub(HVX_Vector Vu, HVX_Vector Vv)
@@ -204,9 +171,7 @@
    ========================================================================== */
 
 #define Q6_Vub_vabsdiff_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffub)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.uh=vabsdiff(Vu32.uh,Vv32.uh)
    C Intrinsic Prototype: HVX_Vector Q6_Vuh_vabsdiff_VuhVuh(HVX_Vector Vu, HVX_Vector Vv)
@@ -215,9 +180,7 @@
    ========================================================================== */
 
 #define Q6_Vuh_vabsdiff_VuhVuh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffuh)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.uw=vabsdiff(Vu32.w,Vv32.w)
    C Intrinsic Prototype: HVX_Vector Q6_Vuw_vabsdiff_VwVw(HVX_Vector Vu, HVX_Vector Vv)
@@ -226,9 +189,7 @@
    ========================================================================== */
 
 #define Q6_Vuw_vabsdiff_VwVw(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsdiffw)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.h=vabs(Vu32.h)
    C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh(HVX_Vector Vu)
@@ -237,9 +198,7 @@
    ========================================================================== */
 
 #define Q6_Vh_vabs_Vh(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh)(Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.h=vabs(Vu32.h):sat
    C Intrinsic Prototype: HVX_Vector Q6_Vh_vabs_Vh_sat(HVX_Vector Vu)
@@ -248,9 +207,7 @@
    ========================================================================== */
 
 #define Q6_Vh_vabs_Vh_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsh_sat)(Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.w=vabs(Vu32.w)
    C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw(HVX_Vector Vu)
@@ -259,9 +216,7 @@
    ========================================================================== */
 
 #define Q6_Vw_vabs_Vw(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw)(Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.w=vabs(Vu32.w):sat
    C Intrinsic Prototype: HVX_Vector Q6_Vw_vabs_Vw_sat(HVX_Vector Vu)
@@ -270,9 +225,7 @@
    ========================================================================== */
 
 #define Q6_Vw_vabs_Vw_sat(Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vabsw_sat)(Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.b=vadd(Vu32.b,Vv32.b)
    C Intrinsic Prototype: HVX_Vector Q6_Vb_vadd_VbVb(HVX_Vector Vu, HVX_Vector Vv)
@@ -281,9 +234,7 @@
    ========================================================================== */
 
 #define Q6_Vb_vadd_VbVb(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vdd32.b=vadd(Vuu32.b,Vvv32.b)
    C Intrinsic Prototype: HVX_VectorPair Q6_Wb_vadd_WbWb(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
@@ -292,9 +243,7 @@
    ========================================================================== */
 
 #define Q6_Wb_vadd_WbWb(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddb_dv)(Vuu,Vvv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (!Qv4) Vx32.b+=Vu32.b
    C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QnVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
@@ -303,9 +252,7 @@
    ========================================================================== */
 
 #define Q6_Vb_condacc_QnVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (Qv4) Vx32.b+=Vu32.b
    C Intrinsic Prototype: HVX_Vector Q6_Vb_condacc_QVbVb(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
@@ -314,9 +261,7 @@
    ========================================================================== */
 
 #define Q6_Vb_condacc_QVbVb(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddbq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.h=vadd(Vu32.h,Vv32.h)
    C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv)
@@ -325,9 +270,7 @@
    ========================================================================== */
 
 #define Q6_Vh_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vdd32.h=vadd(Vuu32.h,Vvv32.h)
    C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
@@ -336,9 +279,7 @@
    ========================================================================== */
 
 #define Q6_Wh_vadd_WhWh(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddh_dv)(Vuu,Vvv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (!Qv4) Vx32.h+=Vu32.h
    C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QnVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
@@ -347,9 +288,7 @@
    ========================================================================== */
 
 #define Q6_Vh_condacc_QnVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhnq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       if (Qv4) Vx32.h+=Vu32.h
    C Intrinsic Prototype: HVX_Vector Q6_Vh_condacc_QVhVh(HVX_VectorPred Qv, HVX_Vector Vx, HVX_Vector Vu)
@@ -358,9 +297,7 @@
    ========================================================================== */
 
 #define Q6_Vh_condacc_QVhVh(Qv,Vx,Vu) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhq)(__BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vandvrt)((Qv),-1),Vx,Vu)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.h=vadd(Vu32.h,Vv32.h):sat
    C Intrinsic Prototype: HVX_Vector Q6_Vh_vadd_VhVh_sat(HVX_Vector Vu, HVX_Vector Vv)
@@ -369,9 +306,7 @@
    ========================================================================== */
 
 #define Q6_Vh_vadd_VhVh_sat(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vdd32.h=vadd(Vuu32.h,Vvv32.h):sat
    C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_WhWh_sat(HVX_VectorPair Vuu, HVX_VectorPair Vvv)
@@ -380,9 +315,7 @@
    ========================================================================== */
 
 #define Q6_Wh_vadd_WhWh_sat(Vuu,Vvv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhsat_dv)(Vuu,Vvv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vdd32.w=vadd(Vu32.h,Vv32.h)
    C Intrinsic Prototype: HVX_VectorPair Q6_Ww_vadd_VhVh(HVX_Vector Vu, HVX_Vector Vv)
@@ -391,9 +324,7 @@
    ========================================================================== */
 
 #define Q6_Ww_vadd_VhVh(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddhw)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vdd32.h=vadd(Vu32.ub,Vv32.ub)
    C Intrinsic Prototype: HVX_VectorPair Q6_Wh_vadd_VubVub(HVX_Vector Vu, HVX_Vector Vv)
@@ -402,9 +333,7 @@
    ========================================================================== */
 
 #define Q6_Wh_vadd_VubVub(Vu,Vv) __BUILTIN_VECTOR_WRAP(__builtin_HEXAGON_V6_vaddubh)(Vu,Vv)
-#endif /* __HEXAGON_ARCH___ >= 60 */
 
-#if __HVX_ARCH__ >= 60
 /* ==========================================================================
    Assembly Syntax:       Vd32.ub=vadd(Vu32.ub,Vv32.ub):sat
    C Intrinsic Prototype: HVX_Vector Q6_Vub_vadd_VubVub_sat(HVX_Vector Vu, HVX_Vector Vv)
@@ -413,9 +342,7 @@
    ===============================================...
[truncated]

dyung · 2026-03-17T07:57:44Z

@androm3da my main concern with this change is that the header file changes could introduce an ABI break which we do not want to do. To me it looks like the header file changes just define additional macros on some versions of the architecture that previously did not. Is that correct?

And can you confirm that this is not introducing an ABI break?

dyung · 2026-03-23T02:58:16Z

ping @androm3da

androm3da · 2026-03-23T14:44:05Z

@androm3da my main concern with this change is that the header file changes could introduce an ABI break which we do not want to do. To me it looks like the header file changes just define additional macros on some versions of the architecture that previously did not. Is that correct?

That is correct. Further: the macros are defining architecture-specific intrinsics. And in this case, the header file changes are becoming stricter on the conditions when those are defined.

And can you confirm that this is not introducing an ABI break?

I ... don't think so. Is there even an ABI for architecture-specific intrinsics?

But let me try and speculate on how things could go wrong here. A program being incorrectly built with the 22.1.0 clang via --target hexagon-linux-musl -mv73 -mhvx but leveraging IEEE FP opcodes via intrinsics would previously get compiled successfully. That same program again built with 22.1.3 clang via --target hexagon-linux-musl -mv73 -mhvx (incorrectly omitting -mhvx-ieee-fp) would get an error.

I guess this is the kind of breakage you might be concerned about, but I see it not as ABI conformance/non-conformance but instead the compiler correctly diagnosing where it previously did not. Do we have a precedent for/against making the compiler stricter in a patch release?

AaronBallman · 2026-03-27T11:55:22Z

clang/lib/Basic/Targets/Hexagon.h

  bool HasHVX = false;
  bool HasHVX64B = false;
  bool HasHVX128B = false;
+  bool HasHVXIeeeFp = false;


I believe this changes the ABI of the HexagonTargetInfo class which is exported with library visibility.

This class isn't part of the public interface of libclang-cpp, and "library visibility" means "visible only inside the library"; see https://github.com/llvm/llvm-project/blob/llvmorg-22.1.2/llvm/include/llvm/Support/Compiler.h#L107-L154:

LLVM_LIBRARY_VISIBILITY - If a class marked with this attribute is linked into a shared library, then the class should be private to the library and not accessible from outside it.

Whoops, thank you for clarifying! It does change the class layout, but not at an expected ABI boundary.

AaronBallman · 2026-03-27T11:57:31Z

clang/lib/Basic/Targets/Hexagon.cpp

      .Case("hvx", HasHVX)
      .Case("hvx-length64b", HasHVX64B)
      .Case("hvx-length128b", HasHVX128B)
+      .Case("hvx-ieee-fp", HasHVXIeeeFp)


Is this backporting a new feature or is it backporting work already in progress on 22.x?

The hvx-ieee-fp feature was introduced in f766bc0 which was available in LLVM 14.0.0.

c-rhodes · 2026-03-30T14:16:36Z

it seems like the concerns around this introducing an ABI break and other comments/questions have been addressed and this is ok to go in, so will backport in coming days unless there's any further comments by then

aankit-ca and others added 2 commits March 6, 2026 06:35

[Hexagon] Define __HVX_IEEE_FP__ when -mhvx-ieee-fp is enabled (llvm#…

de9b26f

…183829) Add a __HVX_IEEE_FP__ define when the compiler is invoked with -mhvx-ieee-fp flag

androm3da requested review from dyung and quic-akaryaki March 6, 2026 14:47

llvmbot added clang Clang issues not falling into any other category backend:Hexagon backend:X86 clang:frontend Language frontend issues, e.g. anything involving "Sema" clang:headers Headers provided by Clang, e.g. for intrinsics labels Mar 6, 2026

androm3da mentioned this pull request Mar 6, 2026

release/22.x: [Hexagon] Define __HVX_IEEE_FP__ when -mhvx-ieee-fp is enabled (#183829) #183978

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dyung added this to the LLVM 22.x Release milestone Mar 6, 2026

github-project-automation bot added this to LLVM Release Status Mar 6, 2026

github-project-automation bot moved this to Needs Triage in LLVM Release Status Mar 6, 2026

dyung moved this from Needs Triage to Needs Review in LLVM Release Status Mar 6, 2026

quic-akaryaki approved these changes Mar 6, 2026

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github-project-automation bot moved this from Needs Review to Needs Merge in LLVM Release Status Mar 6, 2026

androm3da changed the title ~~[Hexagon] Define __HVX_IEEE_FP__ ; Use __HVX_IEEE_FP__ to guard protos~~ release/22.x: [Hexagon] Define __HVX_IEEE_FP__ ; Use __HVX_IEEE_FP__ to guard protos Mar 8, 2026

androm3da mentioned this pull request Mar 11, 2026

[hexagon] clang does not provide HVX IEEE define ; intrinsics are not guarded with a define #183746

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AaronBallman reviewed Mar 27, 2026

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androm3da commented Mar 23, 2026 •

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