Adding arty support for minion.

[nchronas]

To Do before merging:

• Add an example program for the arty (blink LEDs and transmit a message through the UART).
• Add clk_wiz_1 (sd_clk_wiz) IP for SD clock generation.

[nchronas]

Example program in PR.
clk_wiz_1 IP will not be added in the repo.

Tested in arty.

[asb]

Shouldn't top_arty.sv be in pulpino/fpga/rtl? It might be better named arty_top.sv for consistency with nexys_top.sv.

[nchronas]

I named & placed the file, based on the this file.

I think the files found in pulpino/fpga/rtl folder, are taken for the original pulpino core, and are not suitlabe for the minion_soc.

There isn't a problem, rename and or moving it to a different place.
Let me know what you want me to do.

[asb]

Thanks, looks like it's my mistake and that file is best left where it is, unless Jonathan disagrees.

[jrrk]

pulpino/fpga/rtl appears to be a zync specific adaptor layer. Along with a lot of other superfluous files it could be removed from our version of the repository. Since I don't have an Arty, I cannot comment further.