Added minimal example program

[nchronas]

A minimal example for minion, based on the hello and bootstrap software, with serial usage and led blink.

Needs testing on hardware

[asb]

Thanks Nik. Did you mean to include code.v?

[nchronas]

Yes, the example is designed with the intention to be used in hardware. Also the code.v and data.v will be used in the Arty port.

[jrrk]

I think the point was code.v and data.v are output files that, while needed for synthesis, are not in the preferred form for modification. Instead you give instructions for how to generate code.v and data.v from C source and compiler build instructions if needed.

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On 22/08/17 11:48, nchronas wrote: Yes, the example is designed with the intention to be used in hardware. Also the code.v and data.v will be used in the Arty port. — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#7 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AAgF11MfGSil_LmbX1iAbl7-Jg7MIjbmks5sarHhgaJpZM4O-Q8B>.

[asb]

That's what I was thinking, but I now see that software/bootstrap/ has code.v and data.v checked in. The main advantage of having these generated files checked in would be to remove the ocaml dependency. But given code.v and data.v are effectively binaries, they should really be distributed with appropriate copyright notices for any code that is linked in (e.g. newlib). I suggest we don't include generated code.v and data.v files in the repo, and move the rom generators to Python if the ocaml dependency proves to be a barrier.

[nchronas]

I will then remove the code.v and data.v from the PR.

[nchronas]

Tested on arty, with the minimal C program and working.

I modified the one_hot_rdata[3] by replacing the uart_wrcount with a wire that subtracks the FIFO read and write counts, so the FIFO available bytes are shown.

[asb]

The C code looks good to me. Jonathan, are you happy with the Verilog change?

[jrrk]

I don't think the bootstrap directory depends on newlib, it would be far too big. The benefit of having binaries checked in is that an FPGA build may be achieved without having the special Pulpino toolchain installed. The lowrisc_chip uses this technique as well to provide an initial boot.bin

[asb]

No, the bootstrap program supplies its own minimal implementations of libc functions it needs. I can see the argument for reducing the dependency on other software, so we can certainly add code.v and data.v back in to this PR.

Are you happy with the verilog change?

[jrrk]

The minion subsystem, when instantiated in Rocket, does not use the UART, since it would conflict with the trace debugger. Therefore we can safely change the details of the UART Verilog API to match the nchronas implementation. I can't really comment on the software element due to a lack of familiarity with RISCV assembly language.