WIP: code generation for minion SoC

[nchronas]

Code generation for the minion SoC. The generator reads the configuration from a json file and creates the minion_soc.sv with the peripherals defined from the configuration.
Using python and jinja2 for the templating engine.

ToDo:
testing
whitespace issue

[wsong83]

Well, this is interesting and potentially can be very useful.
So the upstream Rocket-chip can generate device tree in the jason format.
For lowRISC, we might need exactly what you proposed here.
So all peripherals emulated by minions can be added to Rocket's device tree therefore their address spaces are regulated directly inside L1 D$. To achieve this, the Chisel Rocket must share the same parameters along with the SV minions. One way to do it, is to ask Chisel to dump parameters then SV reads the parameters. A better way would be: Chisel generate all the peripheral emulated by minions in a jason file and then minion generator generates a proper minion system according to this jason file.

Would it be possible that you can adopt the device tree like format in this jason file? See the jason file generated by github.com/freechipsproject/rocket-chip

[asb]

Thanks for prototyping this Nik.

Hi Wei, could you please paste an example rocket-generated JSON file to gist.github.com or similar?

[nchronas]

I cant think of any issues with adopting a different format. As Alex said if you can share an example JSON file so I would take a closer look.

One of the configuration options I would like to have is to generate a minion SoC with multiple different cores. It would be possible to define the different cores from the device tree?

[wsong83]

The jason file generated is a little bit ugly but for machine to read, who cares.

{"#address-cells":[1],"#size-cells":[1],"compatible":["freechips,rocketchip-unknown-dev"],"cpus":{"#address-cells":[1],"#size-cells":[0],"cpu@0":{"clock-frequency":[0],"compatible":["sifive,rocket0","riscv"],"d-cache-block-size":[64],"d-cache-sets":[64],"d-cache-size":[16384],"d-tlb-sets":[1],"d-tlb-size":[32],"device_type":["cpu"],"i-cache-block-size":[64],"i-cache-sets":[64],"i-cache-size":[16384],"i-tlb-sets":[1],"i-tlb-size":[32],"interrupt-controller":{"#interrupt-cells":[1],"compatible":["riscv,cpu-intc"],"interrupt-controller":[]},"mmu-type":["riscv,sv39"],"next-level-cache":["&/soc/error-device@3000","&/memory@80000000"],"reg":[0],"riscv,isa":["rv64imafdc"],"status":["okay"],"tlb-split":[]},"timebase-frequency":[1000000]},"memory@80000000":{"device_type":["memory"],"reg":[{"base":2147483648,"size":268435456,"r":true,"w":true,"x":true,"c":true}]},"model":["freechips,rocketchip-unknown"],"soc":{"#address-cells":[1],"#size-cells":[1],"clint@2000000":{"compatible":["riscv,clint0"],"interrupts-extended":["&/cpus/cpu@0/interrupt-controller",3,"&/cpus/cpu@0/interrupt-controller",7],"reg":[{"base":33554432,"size":65536,"r":true,"w":true,"x":false,"c":false}],"reg-names":["control"]},"compatible":["freechips,rocketchip-unknown-soc","simple-bus"],"debug-controller@0":{"compatible":["sifive,debug-013","riscv,debug-013"],"interrupts-extended":["&/cpus/cpu@0/interrupt-controller",65535],"reg":[{"base":0,"size":4096,"r":true,"w":true,"x":true,"c":false}],"reg-names":["control"]},"error-device@3000":{"compatible":["sifive,error0"],"reg":[{"base":12288,"size":4096,"r":true,"w":true,"x":false,"c":true}],"reg-names":["mem"]},"external-interrupts":{"interrupt-parent":["&/soc/interrupt-controller@c000000"],"interrupts":[1,2]},"interrupt-controller@c000000":{"#interrupt-cells":[1],"compatible":["riscv,plic0"],"interrupt-controller":[],"interrupts-extended":["&/cpus/cpu@0/interrupt-controller",11,"&/cpus/cpu@0/interrupt-controller",9],"reg":[{"base":201326592,"size":67108864,"r":true,"w":true,"x":false,"c":false}],"reg-names":["control"],"riscv,max-priority":[7],"riscv,ndev":[2]},"mmio@60000000":{"#address-cells":[1],"#size-cells":[1],"compatible":["simple-bus"],"ranges":[{"base":1610612736,"size":536870912,"offset":0,"r":true,"w":true,"x":true,"c":false}]},"ranges":[]}}

A more readable format is the device tree:

/dts-v1/;

/ {
        #address-cells = <1>;
        #size-cells = <1>;
        compatible = "freechips,rocketchip-unknown-dev";
        model = "freechips,rocketchip-unknown";
        L2: cpus {
                #address-cells = <1>;
                #size-cells = <0>;
                timebase-frequency = <1000000>;
                L7: cpu@0 {
                        clock-frequency = <0>;
                        compatible = "sifive,rocket0", "riscv";
                        d-cache-block-size = <64>;
                        d-cache-sets = <64>;
                        d-cache-size = <16384>;
                        d-tlb-sets = <1>;
                        d-tlb-size = <32>;
                        device_type = "cpu";
                        i-cache-block-size = <64>;
                        i-cache-sets = <64>;
                        i-cache-size = <16384>;
                        i-tlb-sets = <1>;
                        i-tlb-size = <32>;
                        mmu-type = "riscv,sv39";
                        next-level-cache = <&L12 &L10>;
                        reg = <0>;
                        riscv,isa = "rv64imafdc";
                        status = "okay";
                        tlb-split;
                        L8: interrupt-controller {
                                #interrupt-cells = <1>;
                                compatible = "riscv,cpu-intc";
                                interrupt-controller;
                        };
                };
        };
        L10: memory@80000000 {
                device_type = "memory";
                reg = <0x80000000 0x10000000>;
        };
        L1: soc {
                #address-cells = <1>;
                #size-cells = <1>;
                compatible = "freechips,rocketchip-unknown-soc", "simple-bus";
                ranges;
                L4: clint@2000000 {
                        compatible = "riscv,clint0";
                        interrupts-extended = <&L8 3 &L8 7>;
                        reg = <0x2000000 0x10000>;
                        reg-names = "control";
                };
                };
                L5: debug-controller@0 {
                        compatible = "sifive,debug-013", "riscv,debug-013";
                        interrupts-extended = <&L8 65535>;
                        reg = <0x0 0x1000>;
                        reg-names = "control";
                };
                L12: error-device@3000 {
                        compatible = "sifive,error0";
                        reg = <0x3000 0x1000>;
                        reg-names = "mem";
                };
                L9: external-interrupts {
                        interrupt-parent = <&L3>;
                        interrupts = <1 2>;
                };
                L3: interrupt-controller@c000000 {
                        #interrupt-cells = <1>;
                        compatible = "riscv,plic0";
                        interrupt-controller;
                        interrupts-extended = <&L8 11 &L8 9>;
                        reg = <0xc000000 0x4000000>;
                        reg-names = "control";
                        riscv,max-priority = <7>;
                        riscv,ndev = <2>;
                };
                L11: mmio@60000000 {
                        #address-cells = <1>;
                        #size-cells = <1>;
                        compatible = "simple-bus";
                        ranges = <0x60000000 0x60000000 0x20000000>;
                };
        };
};

[wsong83]

The minion generator either read a specific part of this jason or the Chisel can generate a partial jason for minions.

Device tree definitely can express heterogeneous multicore systems. However, express the configuration to the Rocket-chip and produce the right json and hardware interface need magic.

[asb]

A pretty-printed form of the above JSON is included below. Ensuring we can represent the information needed by Rocket-chip is definitely a design goal. We have flexibility to use a different JSON format if desired, as long as this information can be extracted. The JSON format used in this pull request is somewhat higher level, which had advantages and disadvantages.

Nik: documentation on GSoC work and developing the other WIP pull requests is higher priority than experimenting with the JSON format here I think.

{
  "#address-cells": [
    1
  ],
  "#size-cells": [
    1
  ],
  "compatible": [
    "freechips,rocketchip-unknown-dev"
  ],
  "cpus": {
    "#address-cells": [
      1
    ],
    "#size-cells": [
      0
    ],
    "cpu@0": {
      "clock-frequency": [
        0
      ],
      "compatible": [
        "sifive,rocket0",
        "riscv"
      ],
      "d-cache-block-size": [
        64
      ],
      "d-cache-sets": [
        64
      ],
      "d-cache-size": [
        16384
      ],
      "d-tlb-sets": [
        1
      ],
      "d-tlb-size": [
        32
      ],
      "device_type": [
        "cpu"
      ],
      "i-cache-block-size": [
        64
      ],
      "i-cache-sets": [
        64
      ],
      "i-cache-size": [
        16384
      ],
      "i-tlb-sets": [
        1
      ],
      "i-tlb-size": [
        32
      ],
      "interrupt-controller": {
        "#interrupt-cells": [
          1
        ],
        "compatible": [
          "riscv,cpu-intc"
        ],
        "interrupt-controller": []
      },
      "mmu-type": [
        "riscv,sv39"
      ],
      "next-level-cache": [
        "&/soc/error-device@3000",
        "&/memory@80000000"
      ],
      "reg": [
        0
      ],
      "riscv,isa": [
        "rv64imafdc"
      ],
      "status": [
        "okay"
      ],
      "tlb-split": []
    },
    "timebase-frequency": [
      1000000
    ]
  },
  "memory@80000000": {
    "device_type": [
      "memory"
    ],
    "reg": [
      {
        "base": 2147483648,
        "size": 268435456,
        "r": true,
        "w": true,
        "x": true,
        "c": true
      }
    ]
  },
  "model": [
    "freechips,rocketchip-unknown"
  ],
  "soc": {
    "#address-cells": [
      1
    ],
    "#size-cells": [
      1
    ],
    "clint@2000000": {
      "compatible": [
        "riscv,clint0"
      ],
      "interrupts-extended": [
        "&/cpus/cpu@0/interrupt-controller",
        3,
        "&/cpus/cpu@0/interrupt-controller",
        7
      ],
      "reg": [
        {
          "base": 33554432,
          "size": 65536,
          "r": true,
          "w": true,
          "x": false,
          "c": false
        }
      ],
      "reg-names": [
        "control"
      ]
    },
    "compatible": [
      "freechips,rocketchip-unknown-soc",
      "simple-bus"
    ],
    "debug-controller@0": {
      "compatible": [
        "sifive,debug-013",
        "riscv,debug-013"
      ],
      "interrupts-extended": [
        "&/cpus/cpu@0/interrupt-controller",
        65535
      ],
      "reg": [
        {
          "base": 0,
          "size": 4096,
          "r": true,
          "w": true,
          "x": true,
          "c": false
        }
      ],
      "reg-names": [
        "control"
      ]
    },
    "error-device@3000": {
      "compatible": [
        "sifive,error0"
      ],
      "reg": [
        {
          "base": 12288,
          "size": 4096,
          "r": true,
          "w": true,
          "x": false,
          "c": true
        }
      ],
      "reg-names": [
        "mem"
      ]
    },
    "external-interrupts": {
      "interrupt-parent": [
        "&/soc/interrupt-controller@c000000"
      ],
      "interrupts": [
        1,
        2
      ]
    },
    "interrupt-controller@c000000": {
      "#interrupt-cells": [
        1
      ],
      "compatible": [
        "riscv,plic0"
      ],
      "interrupt-controller": [],
      "interrupts-extended": [
        "&/cpus/cpu@0/interrupt-controller",
        11,
        "&/cpus/cpu@0/interrupt-controller",
        9
      ],
      "reg": [
        {
          "base": 201326592,
          "size": 67108864,
          "r": true,
          "w": true,
          "x": false,
          "c": false
        }
      ],
      "reg-names": [
        "control"
      ],
      "riscv,max-priority": [
        7
      ],
      "riscv,ndev": [
        2
      ]
    },
    "mmio@60000000": {
      "#address-cells": [
        1
      ],
      "#size-cells": [
        1
      ],
      "compatible": [
        "simple-bus"
      ],
      "ranges": [
        {
          "base": 1610612736,
          "size": 536870912,
          "offset": 0,
          "r": true,
          "w": true,
          "x": true,
          "c": false
        }
      ]
    },
    "ranges": []
  }
}