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manavshah-28/README.md

Welcome to MANAV SHAH's Git page

About

  • 🎓 MS Computer Engineering, Virginia Tech.

  • 🎓 B-Tech in Electronics and Telecommunication Engineering, Veermata Jijabai Technological Institute.

  • 🏆 Winner of Smart India Hackathon 2023 (Hardware edition)

  • 💼 Ex VYOMA Systems RISCV V Verification Intern.

Publication

IEEE ANTS 2023: Reliable key generation for authentication and encryption using RO PUF on FPGA

Research Interests

  • Digital Design and Verification
  • Hardware Descriptive Languages - Verilog / VHDL.
  • anythihg and everything on FPGAs.

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  1. MasterSilicon.github.io MasterSilicon.github.io Public

    HTML

  2. Custom-JTAG-Driven-DFT-Architecture Custom-JTAG-Driven-DFT-Architecture Public

    SystemVerilog

  3. -RiScKy- -RiScKy- Public

    Development of a RISC-V core in Verilog.

    SystemVerilog 4

  4. Cache- Cache- Public

    SystemVerilog

  5. FPGA-based-2-player-Volleyball-Game FPGA-based-2-player-Volleyball-Game Public

    This project recreates a classic volleyball game inspired by Blobby Volley, implemented entirely on an FPGA using the DE1-SoC board and displayed through a VGA monitor. The two players — stylized a…

    SystemVerilog

  6. Ubuntu_Dual_Boot Ubuntu_Dual_Boot Public

    Windows 11 and ubuntu dual booting procedure