16-bit ALU RTL Implementation

Project Overview

This repository contains a complete RTL implementation of a 16-bit Arithmetic Logic Unit (ALU) in SystemVerilog, along with comprehensive verification infrastructure.

Features

• Full 16-bit ALU Implementation: Complete RTL design with modular architecture
• 16 Operations Supported: Arithmetic, logic, shift, and comparison operations
• Comprehensive Testbench: 1017 test cases covering all operations
• 100% Test Pass Rate: All operations fully verified
• Synthesizable Design: Clean RTL code following industry best practices

Directory Structure

.
├── rtl/                    # RTL source files
│   ├── alu_16bit_top.sv   # Top-level ALU module
│   ├── arithmetic/         # Arithmetic unit
│   ├── logic/             # Logic unit
│   ├── shift/             # Shift unit
│   ├── control/           # Control decoder
│   ├── mux/               # Result multiplexer
│   ├── flags/             # Flag generator
│   └── common/            # Package definitions
├── tb/                     # Testbench files
│   ├── alu_16bit_tb.sv    # Main testbench
│   └── test_vectors.txt    # Test vector file
├── docs/                   # Documentation
│   └── block_diagram/      # Modular documentation
├── sim/                    # Simulation outputs
└── Makefile               # Build and simulation scripts

Supported Operations

OpCode	Operation	Description
0x0	ADD	Addition (A + B)
0x1	SUB	Subtraction (A - B)
0x2	INC	Increment (A + 1)
0x3	DEC	Decrement (A - 1)
0x4	AND	Bitwise AND
0x5	OR	Bitwise OR
0x6	XOR	Bitwise XOR
0x7	NOT	Bitwise NOT
0x8	SHL	Shift Left
0x9	SHR	Shift Right
0xA	SAR	Arithmetic Shift Right
0xB	ROL	Rotate Left
0xC	ROR	Rotate Right
0xD	CMP	Compare
0xE	TST	Test (AND without storing)
0xF	CLR	Clear (output zero)

Quick Start

Prerequisites

• Icarus Verilog (iverilog) for simulation
• GTKWave for waveform viewing (optional)
• Make utility

Running Simulation

# Run complete simulation
make sim

# View waveforms
make wave

# Clean build artifacts
make clean

Test Results

Latest test run results:

Total Tests:  1017
Passed:       1017
Failed:       0
Status:       PASSED

Version History

• v1.1.0 - Complete RTL implementation with comprehensive testing
• v1.0.0 - Initial project setup and documentation

Architecture Highlights

• Modular Design: Separate functional units for maintainability
• Carry Skip Adder: Optimized arithmetic unit for performance
• Synchronous Design: Registered inputs and outputs
• Flag Generation: Complete status flags (Zero, Carry, Overflow, Negative)

Documentation

Detailed documentation available in docs/block_diagram/:

• System overview and specifications
• Implementation details for each module
• Verification methodology
• Optimization strategies

License

This project is for educational and development purposes.

Contributors

• RTL Generator Agent
• Testbench Specification Generator Agent
• AI-Assisted Development Tools