fix: decrement SP by 3 during reset sequence#549
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mattgodbolt merged 1 commit intomattgodbolt:mainfrom Jan 31, 2026
Merged
fix: decrement SP by 3 during reset sequence#549mattgodbolt merged 1 commit intomattgodbolt:mainfrom
mattgodbolt merged 1 commit intomattgodbolt:mainfrom
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The real 6502 reset sequence reuses the interrupt/BRK logic internally, performing 3 "dummy" stack operations where SP decrements but R/W is held in read mode (no actual writes). This results in SP being 0xFD after reset when starting from 0x00. Added tests for both Cpu6502 and Tube6502 reset methods, covering: - Initial SP after power-on reset - SP decrement on hard and soft reset - Correct wrap-around behavior near zero Fixes mattgodbolt#547
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Love it! thanks so much, and for the tests too 🎉
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Summary
Fixes #547
The real 6502 reset sequence reuses the interrupt/BRK logic internally, performing 3 "dummy" stack operations where SP decrements but R/W is held in read mode (no actual writes). This results in SP being 0xFD after reset when starting from 0x00.
This PR adds the missing SP decrement to both
Cpu6502.reset()andTube6502.reset()methods.Changes
src/6502.js: Addedthis.s = (this.s - 3) & 0xffafter setting PC and I flag in both reset methodstests/unit/test-sp-reset.js: New test file covering SP reset behaviorTest plan