style: modify module's name by common var

Author: maksyuki

rtl/tc_l2/src/main/scala/common/InstConfig.scala

@@ -6,6 +6,7 @@ import chisel3.util._
 trait InstConfig {
   val SoCEna            = false
   val XLen              = 64
+  val InstLen           = 32
   val RegfileNum        = 32
   val FlashStartAddr    = "h0000000030000000".U(XLen.W)
   val SimStartAddr      = "h0000000080000000".U(XLen.W)

rtl/tc_l2/src/main/scala/core/exec/BEU.scala

@@ -3,19 +3,19 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.ConstVal
+import treecorel2.common.{ConstVal, InstConfig}
 
-class BEU extends Module {
+class BEU extends Module with InstConfig {
   val io = IO(new Bundle {
     val isa        = Input(new ISAIO)
     val imm        = Input(new IMMIO)
-    val src1       = Input(UInt(64.W))
-    val src2       = Input(UInt(64.W))
-    val pc         = Input(UInt(64.W))
+    val src1       = Input(UInt(XLen.W))
+    val src2       = Input(UInt(XLen.W))
+    val pc         = Input(UInt(XLen.W))
     val branIdx    = Input(UInt(ConstVal.GHRLen.W))
     val branchInfo = new BRANCHIO
     val branch     = Output(Bool())
-    val tgt        = Output(UInt(64.W))
+    val tgt        = Output(UInt(XLen.W))
   })
 
   protected val beq   = io.isa.BEQ && (io.src1 === io.src2)

rtl/tc_l2/src/main/scala/core/exec/EXU.scala

@@ -29,6 +29,7 @@ class EXU extends Module {
   protected val rs2       = exReg.inst(24, 20)
   protected val wdest     = exReg.wdest
 
+  // handle bypass signal
   protected val bypassMemSrc1En = io.bypassMem.wen && (rs1 === io.bypassMem.wdest) && (rs1 =/= 0.U)
   protected val bypassMemSrc2En = io.bypassMem.wen && (rs2 === io.bypassMem.wdest) && (rs2 =/= 0.U)
   protected val bypassWbSrc1En  = io.bypassWb.wen && (rs1 === io.bypassWb.wdest) && (rs1 =/= 0.U)
@@ -69,15 +70,15 @@ class EXU extends Module {
   protected val link  = SignExt((isa.JAL | isa.JALR).asUInt, 64) & (pc + 4.U)
   protected val auipc = SignExt(isa.AUIPC.asUInt, 64) & (pc + imm.U)
 
-  protected val csrReg = Module(new CSRReg)
+  protected val csrReg     = Module(new CSRReg)
+  protected val csrData    = csrReg.io.data
+  protected val timeIntrEn = csrReg.io.timeIntrEn
+  protected val ecallEn    = csrReg.io.ecallEn
   csrReg.io.globalEn := io.globalEn
   csrReg.io.pc       := pc
   csrReg.io.inst     := Mux(valid, inst, 0x13.U)
   csrReg.io.src      := src1
   csrReg.io.mtip     := io.mtip
-  protected val csrData    = csrReg.io.data
-  protected val timeIntrEn = csrReg.io.timeIntrEn
-  protected val ecallEn    = csrReg.io.ecallEn
 
   io.nxtPC.trap  := valid && (timeIntrEn || ecallEn)
   io.nxtPC.mtvec := csrReg.io.csrState.mtvec

rtl/tc_l2/src/main/scala/core/id/ISADecoder.scala

@@ -3,6 +3,8 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
+object ISADecoder {}
+
 class ISADecoder extends Module {
   val io = IO(new Bundle {
     val inst = Input(UInt(32.W))

rtl/tc_l2/src/main/scala/core/id/ImmExten.scala

@@ -3,9 +3,11 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-class ImmExten extends Module {
+import treecorel2.common.InstConfig
+
+class ImmExten extends Module with InstConfig {
   val io = IO(new Bundle {
-    val inst = Input(UInt(32.W))
+    val inst = Input(UInt(InstLen.W))
     val imm  = Output(new IMMIO)
   })
 
@@ -15,9 +17,9 @@ class ImmExten extends Module {
   protected val U = Cat(io.inst(31, 12), 0.U(12.W))
   protected val J = Cat(io.inst(31), io.inst(19, 12), io.inst(20), io.inst(30, 21), 0.U(1.W))
 
-  io.imm.I := SignExt(I, 64)
-  io.imm.S := SignExt(S, 64)
-  io.imm.B := SignExt(B, 64)
-  io.imm.U := SignExt(U, 64)
-  io.imm.J := SignExt(J, 64)
+  io.imm.I := SignExt(I, XLen)
+  io.imm.S := SignExt(S, XLen)
+  io.imm.B := SignExt(B, XLen)
+  io.imm.U := SignExt(U, XLen)
+  io.imm.J := SignExt(J, XLen)
 }

rtl/tc_l2/src/main/scala/core/ma/LSU.scala

@@ -3,16 +3,18 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-class LSU extends Module {
+import treecorel2.common.InstConfig
+
+class LSU extends Module with InstConfig {
   val io = IO(new Bundle {
     val valid    = Input(Bool())
     val isa      = Input(new ISAIO)
-    val src1     = Input(UInt(64.W))
-    val src2     = Input(UInt(64.W))
+    val src1     = Input(UInt(XLen.W))
+    val src2     = Input(UInt(XLen.W))
     val imm      = Input(new IMMIO)
     val ld       = new LDIO
     val sd       = new SDIO
-    val loadData = Output(UInt(64.W))
+    val loadData = Output(UInt(XLen.W))
   })
 
   protected val ldInstVis = io.isa.LD || io.isa.LW || io.isa.LH || io.isa.LB || io.isa.LWU || io.isa.LHU || io.isa.LBU
@@ -41,6 +43,7 @@ class LSU extends Module {
   protected val lbuData = SignExt(io.isa.LBU.asUInt, 64) & (ZeroExt(bTypeData, 64))
   io.loadData := ldData | lwData | lhData | lbData | lwuData | lhuData | lbuData
 
+  // store signals
   io.sd.en   := io.valid && sdInstVis
   io.sd.addr := io.src1 + io.imm.S
   protected val sdData    = SignExt(io.isa.SD.asUInt, 64) & io.src2

rtl/tc_l2/src/main/scala/core/wb/WBU.scala

@@ -5,16 +5,15 @@ import chisel3.util._
 
 import difftest._
 
-import treecorel2.common.ConstVal
-import treecorel2.common.InstConfig
+import treecorel2.common.{ConstVal, InstConfig}
 
 class WBU extends Module with InstConfig {
   val io = IO(new Bundle {
     val globalEn = Input(Bool())
     val socEn    = Input(Bool())
     val mem2wb   = Flipped(new MEM2WBIO)
     val wbdata   = new WBDATAIO
-    val gpr      = Input(Vec(32, UInt(64.W)))
+    val gpr      = Input(Vec(RegfileNum, UInt(XLen.W)))
   })
 
   protected val wbReg      = RegEnable(io.mem2wb, WireInit(0.U.asTypeOf(new MEM2WBIO())), io.globalEn)
@@ -55,14 +54,14 @@ class WBU extends Module with InstConfig {
   }
 
   // for difftest commit
-  protected val mmioEn        = cvalid
-  protected val csrVis        = isa.CSRRW || isa.CSRRS || isa.CSRRC || isa.CSRRWI || isa.CSRRSI || isa.CSRRCI
-  protected val mcycleVis     = csrVis && (inst(31, 20) === ConstVal.mcycleAddr)
-  protected val mipVis        = csrVis && (inst(31, 20) === ConstVal.mipAddr)
-  protected val timeIntrEnReg = RegEnable(timeIntrEn, false.B, io.globalEn)
-  protected val diffValid     = io.globalEn && (RegEnable(valid, false.B, io.globalEn) || timeIntrEnReg)
-
   if (!SoCEna) {
+    val mmioEn        = cvalid
+    val csrVis        = isa.CSRRW || isa.CSRRS || isa.CSRRC || isa.CSRRWI || isa.CSRRSI || isa.CSRRCI
+    val mcycleVis     = csrVis && (inst(31, 20) === ConstVal.mcycleAddr)
+    val mipVis        = csrVis && (inst(31, 20) === ConstVal.mipAddr)
+    val timeIntrEnReg = RegEnable(timeIntrEn, false.B, io.globalEn)
+    val diffValid     = io.globalEn && (RegEnable(valid, false.B, io.globalEn) || timeIntrEnReg)
+
     val instComm        = Module(new DifftestInstrCommit)
     val archIntRegState = Module(new DifftestArchIntRegState)
     val csrState        = Module(new DifftestCSRState)
@@ -130,6 +129,6 @@ class WBU extends Module with InstConfig {
 
     archFpRegState.io.clock  := clock
     archFpRegState.io.coreid := 0.U
-    archFpRegState.io.fpr    := RegInit(VecInit(Seq.fill(32)(0.U(64.W))))
+    archFpRegState.io.fpr    := RegInit(VecInit(Seq.fill(RegfileNum)(0.U(XLen.W))))
   }
 }