style: modify the instconfig var name

Author: maksyuki

rtl/tc_l2/src/main/scala/axi4/AXI4Bridge.scala

@@ -38,9 +38,9 @@ class AXI4Bridge extends Module with AXI4Config {
     )
   )
 
-  protected val arSize   = Mux(io.socEn, socARSize, diffRWSize)
-  protected val awSize   = Mux(io.socEn, socAWSize, diffRWSize)
-  protected val addrMask = Mux(io.socEn, socAddrMask, difftestAddrMask)
+  protected val arSize   = Mux(io.socEn, socARSize, DiffRWSize)
+  protected val awSize   = Mux(io.socEn, socAWSize, DiffRWSize)
+  protected val addrMask = Mux(io.socEn, SoCAddrMask, DifftestAddrMask)
 
   when(arbiter.io.state === Arbiter.eumAR) {
     io.axi.ar.valid     := true.B

rtl/tc_l2/src/main/scala/axi4/Crossbar.scala

@@ -43,8 +43,8 @@ class Crossbar extends Module with InstConfig {
   }
 
   // because the difftest's logic addr is 0x000000
-  protected val instSize  = Mux(io.socEn, instSoCRSize, instDiffRSize)
-  protected val baseAddr  = Mux(io.socEn, socStartBaseAddr, socStartBaseAddr)
+  protected val instSize  = Mux(io.socEn, InstSoCRSize, InstDiffRSize)
+  protected val baseAddr  = Mux(io.socEn, SoCStartBaseAddr, SoCStartBaseAddr)
   protected val instAddr  = io.core.fetch.addr - baseAddr
   protected val loadAddr  = io.core.ld.addr - baseAddr
   protected val storeAddr = io.core.sd.addr - baseAddr

rtl/tc_l2/src/main/scala/common/InstConfig.scala

@@ -6,15 +6,16 @@ import chisel3.util._
 trait InstConfig {
   val SoCEna            = false
   val XLen              = 64
-  val flashStartAddr    = "h0000000030000000".U(XLen.W)
-  val simStartAddr      = "h0000000080000000".U(XLen.W)
-  val diffStartBaseAddr = "h0000000080000000".U(XLen.W)
-  val socStartBaseAddr  = "h0000000000000000".U(XLen.W)
-  val difftestAddrMask  = "hfffffffffffffff8".U(XLen.W)
-  val socAddrMask       = "hffffffffffffffff".U(XLen.W)
-  val instSoCRSize      = 2.U
-  val instDiffRSize     = 3.U
-  val diffRWSize        = 3.U
+  val RegfileNum        = 32
+  val FlashStartAddr    = "h0000000030000000".U(XLen.W)
+  val SimStartAddr      = "h0000000080000000".U(XLen.W)
+  val DiffStartBaseAddr = "h0000000080000000".U(XLen.W)
+  val SoCStartBaseAddr  = "h0000000000000000".U(XLen.W)
+  val DifftestAddrMask  = "hfffffffffffffff8".U(XLen.W)
+  val SoCAddrMask       = "hffffffffffffffff".U(XLen.W)
+  val InstSoCRSize      = 2.U
+  val InstDiffRSize     = 3.U
+  val DiffRWSize        = 3.U
   val CacheEna          = false
 
   val NWay          = 4

rtl/tc_l2/src/main/scala/core/id/IDU.scala

@@ -3,14 +3,16 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-class IDU extends Module {
+import treecorel2.common.InstConfig
+
+class IDU extends Module with InstConfig {
   val io = IO(new Bundle {
     val globalEn = Input(Bool())
     val stall    = Input(Bool())
     val if2id    = Flipped(new IF2IDIO)
     val wbdata   = Flipped(new WBDATAIO)
     val id2ex    = new ID2EXIO
-    val gpr      = Output(Vec(32, UInt(64.W)))
+    val gpr      = Output(Vec(RegfileNum, UInt(XLen.W)))
   })
 
   protected val idReg     = RegEnable(io.if2id, WireInit(0.U.asTypeOf(new IF2IDIO())), io.globalEn)

rtl/tc_l2/src/main/scala/core/id/RegFile.scala

@@ -3,10 +3,11 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-class RegFile {
-  // public registers
-  val gpr = RegInit(VecInit(Seq.fill(32)(0.U(64.W))))
+import treecorel2.common.InstConfig
 
+class RegFile extends InstConfig {
+  // public registers
+  val gpr = RegInit(VecInit(Seq.fill(RegfileNum)(0.U(XLen.W))))
   // io oper
   def read(addr: UInt): UInt = { gpr(addr) }
   def write(wen: Bool, addr: UInt, data: UInt): Unit = {

rtl/tc_l2/src/main/scala/core/if/IFU.scala

@@ -16,10 +16,10 @@ class IFU extends Module with InstConfig {
     val if2id      = new IF2IDIO
   })
 
-  protected val startAddr = Mux(io.socEn, flashStartAddr, simStartAddr)
+  protected val startAddr = Mux(io.socEn, FlashStartAddr, SimStartAddr)
+  protected val pc        = RegInit(startAddr)
   protected val valid     = Mux(reset.asBool(), false.B, true.B)
   protected val inst      = io.fetch.data
-  protected val pc        = RegInit(startAddr)
 
   protected val bpu = Module(new BPU)
   bpu.io.branchInfo <> io.branchInfo