style: modify axi bridge and arbiter's mask impl

Author: maksyuki

rtl/tc_l2/src/main/scala/axi4/AXI4Bridge.scala

@@ -22,10 +22,9 @@ class AXI4Bridge extends Module with InstConfig {
   arbiter.io.rHdShk   := io.axi.r.fire()
 
   protected val wMask     = arbiter.io.dxchg.wmask
-  protected val byteSize  = wMask(7) + wMask(6) + wMask(5) + wMask(4) + wMask(3) + wMask(2) + wMask(1) + wMask(0)
   protected val socARSize = arbiter.io.dxchg.rsize
   protected val socAWSize = MuxLookup(
-    byteSize,
+    PopCount(wMask),
     0.U,
     Array(
       8.U -> 3.U,

rtl/tc_l2/src/main/scala/axi4/Arbiter.scala

@@ -15,7 +15,7 @@ class Arbiter extends Module with InstConfig {
     val bHdShk   = Input(Bool())
     val arHdShk  = Input(Bool())
     val rHdShk   = Input(Bool())
-    val axirdata = Input(UInt(64.W))
+    val axirdata = Input(UInt(XLen.W))
     val dxchg    = Flipped(new DXCHGIO)
     val state    = Output(UInt(3.W))
     val runEn    = Output(Bool())
@@ -27,13 +27,13 @@ class Arbiter extends Module with InstConfig {
 
   protected val valid    = RegInit(false.B)
   protected val ren      = RegInit(false.B)
-  protected val raddr    = RegInit(0.U(64.W))
-  protected val rdata    = RegInit(0.U(64.W))
+  protected val raddr    = RegInit(0.U(XLen.W))
+  protected val rdata    = RegInit(0.U(XLen.W))
   protected val rsize    = RegInit(0.U(3.W))
   protected val wen      = RegInit(false.B)
-  protected val waddr    = RegInit(0.U(64.W))
-  protected val wdata    = RegInit(0.U(64.W))
-  protected val wmask    = RegInit(0.U(8.W))
+  protected val waddr    = RegInit(0.U(XLen.W))
+  protected val wdata    = RegInit(0.U(XLen.W))
+  protected val wmask    = RegInit(0.U(MaskLen.W))
   protected val stateReg = RegInit(Arbiter.eumIDLE)
   io.state       := stateReg
   io.dxchg.rdata := rdata