refactor: use common params to simplify the codes

Author: maksyuki

rtl/tc_l2/src/main/scala/common/ConstVal.scala

@@ -62,7 +62,7 @@ class TreeCoreL2 extends Module with InstConfig {
 
   // special judge
   protected val lsStall   = RegEnable(cyc1, false.B, io.globalEn) || RegEnable(cyc2, false.B, io.globalEn)
-  protected val ldDataReg = RegInit(0.U(64.W))
+  protected val ldDataReg = RegInit(0.U(XLen.W))
 
   when(io.globalEn) {
     when(cyc1) {

rtl/tc_l2/src/main/scala/core/TreeCoreL2.scala

@@ -41,11 +41,10 @@ class CSRReg extends Module with InstConfig {
     )
   )
 
-  protected val mretVis  = io.inst === instMRET
-  protected val ecallVis = io.inst === instECALL
-  protected val zimm     = ZeroExt(io.inst(19, 15), XLen)
-  protected val addr     = io.inst(31, 20)
-
+  protected val zimm        = ZeroExt(io.inst(19, 15), XLen)
+  protected val addr        = io.inst(31, 20)
+  protected val mretVis     = io.inst === instMRET
+  protected val ecallVis    = io.inst === instECALL
   protected val mhartidVis  = addr === mhartidAddr
   protected val mstatusVis  = addr === mstatusAddr
   protected val mieVis      = addr === mieAddr

rtl/tc_l2/src/main/scala/core/exec/CSRReg.scala

@@ -9,9 +9,9 @@ class BPU extends Module with InstConfig {
   val io = IO(new Bundle {
     val branchInfo = Flipped(new BRANCHIO)
     // predictor interface
-    val lookupPc  = Input(UInt(ConstVal.AddrLen.W))
+    val lookupPc  = Input(UInt(XLen.W))
     val predTaken = Output(Bool())
-    val predTgt   = Output(UInt(ConstVal.AddrLen.W))
+    val predTgt   = Output(UInt(XLen.W))
     val predIdx   = Output(UInt(GHRLen.W))
   })
 

rtl/tc_l2/src/main/scala/core/if/BPU.scala

@@ -3,9 +3,9 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-class BTBLine extends Bundle {
-  val pc   = UInt(ConstVal.AddrLen.W)
-  val tgt  = UInt(ConstVal.AddrLen.W)
+class BTBLine extends Bundle with IOConfig {
+  val pc   = UInt(XLen.W)
+  val tgt  = UInt(XLen.W)
   val jump = Bool()
 }
 
@@ -14,13 +14,13 @@ class BTB extends Module with InstConfig {
     // branch info (from idu)
     val branch = Input(Bool())
     val jump   = Input(Bool())
-    val pc     = Input(UInt(ConstVal.AddrLen.W))
-    val tgt    = Input(UInt(ConstVal.AddrLen.W))
+    val pc     = Input(UInt(XLen.W))
+    val tgt    = Input(UInt(XLen.W))
     // BTB lookup interface
     val lookupBranch = Output(Bool())
     val lookupJump   = Output(Bool())
-    val lookupPc     = Input(UInt(ConstVal.AddrLen.W))
-    val lookupTgt    = Output(UInt(ConstVal.AddrLen.W))
+    val lookupPc     = Input(UInt(XLen.W))
+    val lookupTgt    = Output(UInt(XLen.W))
   })
 
   // definitions of BTB lines and valid bits

rtl/tc_l2/src/main/scala/core/if/BTB.scala

@@ -23,13 +23,13 @@ class LSU extends Module with InstConfig {
 
   protected val ldSize = MuxLookup(
     io.isa,
-    0.U(3.W),
+    0.U(LDSize.W),
     Seq(
-      instLH  -> 1.U(3.W),
-      instLHU -> 1.U(3.W),
-      instLW  -> 2.U(3.W),
-      instLWU -> 2.U(3.W),
-      instLD  -> 3.U(3.W)
+      instLH  -> 1.U(LDSize.W),
+      instLHU -> 1.U(LDSize.W),
+      instLW  -> 2.U(LDSize.W),
+      instLWU -> 2.U(LDSize.W),
+      instLD  -> 3.U(LDSize.W)
     )
   )
   io.ld.size := ldSize
@@ -67,26 +67,22 @@ class LSU extends Module with InstConfig {
     )
   )
 
-  protected val sdMask = MuxLookup(
+  val sdMask = MuxLookup(
     io.isa,
-    0.U(8.W), // NOTE: important!!!
+    0.U(MaskLen.W), // NOTE: important!!!
     Seq(
-      instSD -> "b1111_1111".U(8.W),
-      instSW -> ("b0000_1111".U(8.W) << io.sd.addr(2, 0)),
-      instSH -> ("b0000_0011".U(8.W) << io.sd.addr(2, 0)),
-      instSB -> ("b0000_0001".U(8.W) << io.sd.addr(2, 0))
+      instSD -> "b1111_1111".U(MaskLen.W),
+      instSW -> ("b0000_1111".U(MaskLen.W) << io.sd.addr(2, 0)),
+      instSH -> ("b0000_0011".U(MaskLen.W) << io.sd.addr(2, 0)),
+      instSB -> ("b0000_0001".U(MaskLen.W) << io.sd.addr(2, 0))
     )
   )
 
-  protected val sdMask0   = Mux(sdMask(0).asBool(), "hff".U(8.W), 0.U(8.W))
-  protected val sdMask1   = Mux(sdMask(1).asBool(), "hff".U(8.W), 0.U(8.W))
-  protected val sdMask2   = Mux(sdMask(2).asBool(), "hff".U(8.W), 0.U(8.W))
-  protected val sdMask3   = Mux(sdMask(3).asBool(), "hff".U(8.W), 0.U(8.W))
-  protected val sdMask4   = Mux(sdMask(4).asBool(), "hff".U(8.W), 0.U(8.W))
-  protected val sdMask5   = Mux(sdMask(5).asBool(), "hff".U(8.W), 0.U(8.W))
-  protected val sdMask6   = Mux(sdMask(6).asBool(), "hff".U(8.W), 0.U(8.W))
-  protected val sdMask7   = Mux(sdMask(7).asBool(), "hff".U(8.W), 0.U(8.W))
-  protected val extenMask = Cat(sdMask7, sdMask6, sdMask5, sdMask4, sdMask3, sdMask2, sdMask1, sdMask0)
+  val tmpMask = Wire(Vec(8, UInt((XLen / 8).W)))
+  for (i <- 0 until 8) {
+    tmpMask(i) := Mux(sdMask(i).asBool(), "hff".U((XLen / 8).W), 0.U((XLen / 8).W))
+  }
+  protected val extenMask = tmpMask.asUInt()
 
   io.sd.data := storeData & extenMask
   io.sd.mask := sdMask