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maksyukimaksyuki
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refactor: add hierarchy trait configs to share common params in io bundles
1 parent 7dc4f4d commit 6294041

20 files changed

+132
-119
lines changed

‎rtl/tc_l2/src/main/scala/axi4/AXI4Bridge.scala‎

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,9 @@
1-
package sim
1+
package treecorel2
22

33
import chisel3._
44
import chisel3.util._
55

6-
import treecorel2._
7-
import treecorel2.AXI4Config
8-
9-
class AXI4Bridge extends Module with AXI4Config {
6+
class AXI4Bridge extends Module with InstConfig {
107
val io = IO(new Bundle {
118
val socEn = Input(Bool())
129
val runEn = Output(Bool())

‎rtl/tc_l2/src/main/scala/axi4/Arbiter.scala‎

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,17 +1,14 @@
1-
package sim
1+
package treecorel2
22

33
import chisel3._
44
import chisel3.util._
55

6-
import treecorel2.DXCHGIO
7-
import treecorel2.AXI4Config
8-
96
object Arbiter {
107
// FSM var for read/write
118
val eumIDLE :: eumStandby :: eumIDLE2 :: eumAW :: eumW :: eumB :: eumAR :: eumR :: Nil = Enum(8)
129
}
1310

14-
class Arbiter extends Module with AXI4Config {
11+
class Arbiter extends Module with InstConfig {
1512
val io = IO(new Bundle {
1613
val awHdShk = Input(Bool())
1714
val wHdShk = Input(Bool())

‎rtl/tc_l2/src/main/scala/common/AXI4Config.scala‎

Lines changed: 13 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,4 +3,16 @@ package treecorel2
33
import chisel3._
44
import chisel3.util._
55

6-
trait AXI4Config extends InstConfig {}
6+
trait AXI4Config extends IOConfig {
7+
val AxiProtLen = 3
8+
val AxiIdLen = 4
9+
val AxiUserLen = 1
10+
val AxiSizeLen = 3 // NOTE: or 2?
11+
val AxiLen = 8
12+
val AxiStrb = 8
13+
val AxiBurstLen = 2
14+
val AxiCacheLen = 4
15+
val AxiQosLen = 4
16+
val AxiRegionLen = 4
17+
val AxiRespLen = 2
18+
}

‎rtl/tc_l2/src/main/scala/common/InstConfig.scala‎

Lines changed: 24 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -3,11 +3,28 @@ package treecorel2
33
import chisel3._
44
import chisel3.util._
55

6-
trait InstConfig {
7-
val SoCEna = false
8-
val XLen = 64
9-
val InstLen = 32
10-
val RegfileNum = 32
6+
trait IOConfig {
7+
val XLen = 64
8+
val InstLen = 32
9+
val RegfileLen = 5
10+
val RegfileNum = 1 << RegfileLen
11+
val ISALen = 6
12+
// mem
13+
val MaskLen = 8
14+
val LDSize = 3
15+
// branch prediction
16+
val GHRLen = 5
17+
val PHTSize = 1 << GHRLen
18+
val BTBIdxLen = 5
19+
val BTBPcLen = XLen - BTBIdxLen
20+
val BTBTgtLen = XLen
21+
val BTBSize = 1 << BTBIdxLen
22+
}
23+
24+
trait InstConfig extends IOConfig {
25+
val SoCEna = true
26+
val CacheEna = false
27+
1128
val FlashStartAddr = "h0000000030000000".U(XLen.W)
1229
val SimStartAddr = "h0000000080000000".U(XLen.W)
1330
val DiffStartBaseAddr = "h0000000080000000".U(XLen.W)
@@ -17,8 +34,8 @@ trait InstConfig {
1734
val InstSoCRSize = 2.U
1835
val InstDiffRSize = 3.U
1936
val DiffRWSize = 3.U
20-
val CacheEna = false
21-
val NOPInst = 0x13.U
37+
38+
val NOPInst = 0x13.U
2239
// inst type
2340
// nop is equal to [addi x0, x0, 0], so the oper is same as 'addi' inst
2441
val InstTypeLen = 3
@@ -95,14 +112,6 @@ trait InstConfig {
95112
val instFENCE_I = 59.U(InstValLen.W)
96113
val instCUST = 60.U(InstValLen.W)
97114

98-
// branch prediction
99-
val GHRLen = 5
100-
val PHTSize = 1 << GHRLen
101-
val BTBIdxLen = 5
102-
val BTBPcLen = XLen - BTBIdxLen
103-
val BTBTgtLen = XLen
104-
val BTBSize = 1 << BTBIdxLen
105-
106115
// cache
107116
val NWay = 4
108117
val NBank = 4

‎rtl/tc_l2/src/main/scala/core/Processor.scala‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,9 @@
1-
package sim
1+
package treecorel2
22

33
import chisel3._
44
import chisel3.util._
55

66
import difftest._
7-
import treecorel2._
87

98
class Processor extends Module {
109
val io = IO(new Bundle {

‎rtl/tc_l2/src/main/scala/core/TreeCoreL2.scala‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@ import chisel3._
44
import chisel3.util._
55
import difftest._
66

7-
class TreeCoreL2 extends Module {
7+
class TreeCoreL2 extends Module with InstConfig {
88
val io = IO(new Bundle {
99
val globalEn = Input(Bool())
1010
val socEn = Input(Bool())

‎rtl/tc_l2/src/main/scala/core/if/BTB.scala‎

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,6 @@ package treecorel2
33
import chisel3._
44
import chisel3.util._
55

6-
76
class BTBLine extends Bundle {
87
val pc = UInt(ConstVal.AddrLen.W)
98
val tgt = UInt(ConstVal.AddrLen.W)

‎rtl/tc_l2/src/main/scala/port/AXI4IO.scala‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -3,49 +3,49 @@ package treecorel2
33
import chisel3._
44
import chisel3.util._
55

6-
class SOCAXI4ARWIO extends Bundle {
6+
class SOCAXI4ARWIO extends Bundle with AXI4Config {
77
val addr = Output(UInt(32.W))
8-
val id = Output(UInt(4.W))
9-
val len = Output(UInt(8.W))
10-
val size = Output(UInt(3.W))
11-
val burst = Output(UInt(2.W))
8+
val id = Output(UInt(AxiIdLen.W))
9+
val len = Output(UInt(AxiLen.W))
10+
val size = Output(UInt(AxiSizeLen.W))
11+
val burst = Output(UInt(AxiBurstLen.W))
1212
}
1313

1414
class AXI4ARWIO extends SOCAXI4ARWIO {
15-
override val addr = Output(UInt(64.W))
16-
val prot = Output(UInt(3.W))
17-
val user = Output(UInt(1.W))
15+
override val addr = Output(UInt(XLen.W))
16+
val prot = Output(UInt(AxiProtLen.W))
17+
val user = Output(UInt(AxiUserLen.W))
1818
val lock = Output(Bool())
19-
val cache = Output(UInt(4.W))
20-
val qos = Output(UInt(4.W))
19+
val cache = Output(UInt(AxiCacheLen.W))
20+
val qos = Output(UInt(AxiQosLen.W))
2121
}
2222

23-
class SOCAXI4WIO extends Bundle {
24-
val data = Output(UInt(64.W))
25-
val strb = Output(UInt(8.W))
23+
class SOCAXI4WIO extends Bundle with AXI4Config {
24+
val data = Output(UInt(XLen.W))
25+
val strb = Output(UInt(AxiStrb.W))
2626
val last = Output(Bool())
2727
}
2828

2929
class AXI4WIO extends SOCAXI4WIO {}
3030

31-
class SOCAXI4BIO extends Bundle {
32-
val resp = Output(UInt(2.W))
33-
val id = Output(UInt(4.W))
31+
class SOCAXI4BIO extends Bundle with AXI4Config {
32+
val resp = Output(UInt(AxiRespLen.W))
33+
val id = Output(UInt(AxiIdLen.W))
3434
}
3535

3636
class AXI4BIO extends SOCAXI4BIO {
37-
val user = Output(UInt(1.W))
37+
val user = Output(UInt(AxiUserLen.W))
3838
}
3939

40-
class SOCAXI4RIO extends Bundle {
41-
val resp = Output(UInt(2.W))
42-
val data = Output(UInt(64.W))
40+
class SOCAXI4RIO extends Bundle with AXI4Config {
41+
val resp = Output(UInt(AxiRespLen.W))
42+
val data = Output(UInt(XLen.W))
4343
val last = Output(Bool())
44-
val id = Output(UInt(4.W))
44+
val id = Output(UInt(AxiIdLen.W))
4545
}
4646

4747
class AXI4RIO extends SOCAXI4RIO {
48-
val user = Output(UInt(1.W))
48+
val user = Output(UInt(AxiUserLen.W))
4949
}
5050

5151
class SOCAXI4IO extends Bundle {

‎rtl/tc_l2/src/main/scala/port/BRANCH.scala‎

Lines changed: 0 additions & 13 deletions
This file was deleted.

‎rtl/tc_l2/src/main/scala/port/BRANCHIO.scala‎

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,13 @@
1+
package treecorel2
2+
3+
import chisel3._
4+
import chisel3.util._
5+
6+
class BRANCHIO extends Bundle with IOConfig {
7+
val branch = Output(Bool()) // prev inst is a b/j
8+
val jump = Output(Bool()) // is 'jal' or 'jalr'
9+
val taken = Output(Bool()) // is prev branch taken
10+
val idx = Output(UInt(GHRLen.W)) // prev idx of PHT(GHRLen)
11+
val pc = Output(UInt(XLen.W)) // prev instruction PC
12+
val tgt = Output(UInt(XLen.W)) // prev branch tgt
13+
}

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