style: modify the core var's name

Author: maksyuki

rtl/tc_l2/src/main/scala/common/InstConfig.scala

@@ -6,6 +6,8 @@ import chisel3.util._
 trait InstConfig {
   val SoCEna            = false
   val XLen              = 64
+  val flashStartAddr    = "h0000000030000000".U(XLen.W)
+  val simStartAddr      = "h0000000080000000".U(XLen.W)
   val diffStartBaseAddr = "h0000000080000000".U(XLen.W)
   val socStartBaseAddr  = "h0000000000000000".U(XLen.W)
   val difftestAddrMask  = "hfffffffffffffff8".U(XLen.W)

rtl/tc_l2/src/main/scala/core/TreeCoreL2.scala

@@ -19,6 +19,8 @@ class TreeCoreL2 extends Module {
   protected val mau = Module(new MAU)
   protected val wbu = Module(new WBU)
 
+  // 1. switch base addr
+  // 2. switch difftest access
   ifu.io.socEn := io.socEn
   wbu.io.socEn := io.socEn
 
@@ -27,62 +29,57 @@ class TreeCoreL2 extends Module {
   idu.io.id2ex  <> exu.io.id2ex
   exu.io.ex2mem <> mau.io.ex2mem
   mau.io.mem2wb <> wbu.io.mem2wb
-
+  // stall signal
   exu.io.stall <> idu.io.stall
   exu.io.stall <> ifu.io.stall
-
   // branch prediction
   ifu.io.branchInfo <> exu.io.branchInfo
-
   // bypass
   idu.io.wbdata    <> wbu.io.wbdata
   exu.io.bypassMem <> mau.io.bypassMem
   exu.io.bypassWb  <> wbu.io.wbdata
-  exu.io.nxtPC     <> ifu.io.nxtPC
-  exu.io.mtip      <> mau.io.mtip
+  // misc
+  idu.io.gpr   <> wbu.io.gpr
+  exu.io.nxtPC <> ifu.io.nxtPC
+  exu.io.mtip  <> mau.io.mtip
 
+  // stall
   protected val isStall            = exu.io.stall
   protected val (tickCnt, cntWrap) = Counter(io.globalEn && isStall, 3)
-  protected val stallCycle1        = isStall && (tickCnt === 0.U)
-  protected val stallCycle2        = isStall && (tickCnt === 1.U)
-  protected val stallCycle3        = isStall && (tickCnt === 2.U)
-
-  ifu.io.stall := stallCycle1
-  idu.io.stall := stallCycle1
+  protected val cyc1               = isStall && (tickCnt === 0.U)
+  protected val cyc2               = isStall && (tickCnt === 1.U)
+  protected val cyc3               = isStall && (tickCnt === 2.U)
 
+  ifu.io.stall    := cyc1
+  idu.io.stall    := cyc1
   ifu.io.globalEn := io.globalEn
   idu.io.globalEn := io.globalEn
-  exu.io.globalEn := Mux(stallCycle1 || stallCycle2, false.B, io.globalEn)
-  mau.io.globalEn := Mux(stallCycle1 || stallCycle2, false.B, io.globalEn)
-  wbu.io.globalEn := Mux(stallCycle1 || stallCycle2, false.B, io.globalEn)
+  exu.io.globalEn := Mux(cyc1 || cyc2, false.B, io.globalEn)
+  mau.io.globalEn := Mux(cyc1 || cyc2, false.B, io.globalEn)
+  wbu.io.globalEn := Mux(cyc1 || cyc2, false.B, io.globalEn)
+  idu.io.wbdata   := Mux(cyc1 || cyc2, 0.U.asTypeOf(new WBDATAIO), wbu.io.wbdata)
+  ifu.io.nxtPC    := Mux(cyc1, exu.io.nxtPC, 0.U.asTypeOf(new NXTPCIO))
 
-  idu.io.wbdata := Mux(stallCycle1 || stallCycle2, 0.U.asTypeOf(new WBDATAIO), wbu.io.wbdata)
-  ifu.io.nxtPC  := Mux(stallCycle1, exu.io.nxtPC, 0.U.asTypeOf(new NXTPCIO))
-
-  protected val ldDataInStall = RegInit(0.U(64.W))
+  // special judge
+  protected val lsStall   = RegEnable(cyc1, false.B, io.globalEn) || RegEnable(cyc2, false.B, io.globalEn)
+  protected val ldDataReg = RegInit(0.U(64.W))
 
   when(io.globalEn) {
-    when(stallCycle1) {
-      ldDataInStall := io.ld.data
-    }.elsewhen(stallCycle3) {
-      ldDataInStall := 0.U
+    when(cyc1) {
+      ldDataReg := io.ld.data
+    }.elsewhen(cyc3) {
+      ldDataReg := 0.U
     }
   }
 
   // communicate with extern io
-  io.fetch <> ifu.io.fetch
-
-  //Even load can change machine state
-  protected val lsStall = RegEnable(stallCycle1, false.B, io.globalEn) || RegEnable(stallCycle2, false.B, io.globalEn)
+  io.fetch       <> ifu.io.fetch
   io.ld.en       := mau.io.ld.en && ~lsStall
   io.ld.addr     := mau.io.ld.addr
-  mau.io.ld.data := Mux(lsStall, ldDataInStall, io.ld.data)
+  mau.io.ld.data := Mux(lsStall, ldDataReg, io.ld.data)
   io.ld.size     := mau.io.ld.size
-
-  io.sd.en   := mau.io.sd.en && ~lsStall
-  io.sd.addr := mau.io.sd.addr
-  io.sd.data := mau.io.sd.data
-  io.sd.mask := mau.io.sd.mask
-
-  idu.io.gpr <> wbu.io.gpr
+  io.sd.en       := mau.io.sd.en && ~lsStall
+  io.sd.addr     := mau.io.sd.addr
+  io.sd.data     := mau.io.sd.data
+  io.sd.mask     := mau.io.sd.mask
 }

rtl/tc_l2/src/main/scala/core/if/IFU.scala

@@ -3,20 +3,20 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.ConstVal
+import treecorel2.common.{ConstVal, InstConfig}
 
-class IFU extends Module {
+class IFU extends Module with InstConfig {
   val io = IO(new Bundle {
     val globalEn   = Input(Bool())
     val stall      = Input(Bool())
     val socEn      = Input(Bool())
     val branchInfo = Flipped(new BRANCHIO)
+    val nxtPC      = Flipped(new NXTPCIO)
     val fetch      = new IFIO
     val if2id      = new IF2IDIO
-    val nxtPC      = Flipped(new NXTPCIO)
   })
 
-  protected val startAddr = Mux(io.socEn, "h0000000030000000".U(64.W), "h0000000080000000".U(64.W))
+  protected val startAddr = Mux(io.socEn, flashStartAddr, simStartAddr)
   protected val valid     = Mux(reset.asBool(), false.B, true.B)
   protected val inst      = io.fetch.data
   protected val pc        = RegInit(startAddr)