refactor: change .common scope var into root scope

maksyuki · maksyuki · commit 7dc4f4d37e1e · 2022-01-21T15:29:19.000+08:00
diff --git a/rtl/tc_l2/src/main/scala/axi4/AXI4Bridge.scala b/rtl/tc_l2/src/main/scala/axi4/AXI4Bridge.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 
 import treecorel2._
-import treecorel2.common.AXI4Config
+import treecorel2.AXI4Config
 
 class AXI4Bridge extends Module with AXI4Config {
   val io = IO(new Bundle {
diff --git a/rtl/tc_l2/src/main/scala/axi4/Arbiter.scala b/rtl/tc_l2/src/main/scala/axi4/Arbiter.scala
@@ -4,7 +4,7 @@ import chisel3._
 import chisel3.util._
 
 import treecorel2.DXCHGIO
-import treecorel2.common.AXI4Config
+import treecorel2.AXI4Config
 
 object Arbiter {
 // FSM var for read/write
diff --git a/rtl/tc_l2/src/main/scala/axi4/Crossbar.scala b/rtl/tc_l2/src/main/scala/axi4/Crossbar.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.InstConfig
-
 class Crossbar extends Module with InstConfig {
   val io = IO(new Bundle {
     val socEn = Input(Bool())
diff --git a/rtl/tc_l2/src/main/scala/common/AXI4Config.scala b/rtl/tc_l2/src/main/scala/common/AXI4Config.scala
@@ -1,4 +1,4 @@
-package treecorel2.common
+package treecorel2
 
 import chisel3._
 import chisel3.util._
diff --git a/rtl/tc_l2/src/main/scala/common/ConstVal.scala b/rtl/tc_l2/src/main/scala/common/ConstVal.scala
@@ -1,4 +1,4 @@
-package treecorel2.common
+package treecorel2
 
 import chisel3._
 import chisel3.util.log2Ceil
diff --git a/rtl/tc_l2/src/main/scala/common/InstConfig.scala b/rtl/tc_l2/src/main/scala/common/InstConfig.scala
@@ -1,4 +1,4 @@
-package treecorel2.common
+package treecorel2
 
 import chisel3._
 import chisel3.util._
diff --git a/rtl/tc_l2/src/main/scala/core/exec/ACU.scala b/rtl/tc_l2/src/main/scala/core/exec/ACU.scala
@@ -3,7 +3,7 @@
 // import chisel3._
 // import chisel3.util._
 
-// import treecorel2.common.ConstVal
+// import treecorel2.ConstVal
 
 // class AGU extends Module {
 //   val io = IO(new Bundle {
diff --git a/rtl/tc_l2/src/main/scala/core/exec/ALU.scala b/rtl/tc_l2/src/main/scala/core/exec/ALU.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.InstConfig
-
 class ALU extends Module with InstConfig {
   val io = IO(new Bundle {
     val isa  = Input(UInt(InstValLen.W))
diff --git a/rtl/tc_l2/src/main/scala/core/exec/BEU.scala b/rtl/tc_l2/src/main/scala/core/exec/BEU.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.InstConfig
-
 class BEU extends Module with InstConfig {
   val io = IO(new Bundle {
     val isa        = Input(UInt(InstValLen.W))
diff --git a/rtl/tc_l2/src/main/scala/core/exec/CSRReg.scala b/rtl/tc_l2/src/main/scala/core/exec/CSRReg.scala
@@ -4,8 +4,6 @@ import chisel3._
 import chisel3.util._
 import difftest._
 
-import treecorel2.common.InstConfig
-
 class CSRReg extends Module with InstConfig {
   val io = IO(new Bundle {
     val globalEn   = Input(Bool())
diff --git a/rtl/tc_l2/src/main/scala/core/exec/EXU.scala b/rtl/tc_l2/src/main/scala/core/exec/EXU.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.InstConfig
-
 class EXU extends Module with InstConfig {
   val io = IO(new Bundle {
     val globalEn   = Input(Bool())
diff --git a/rtl/tc_l2/src/main/scala/core/id/IDU.scala b/rtl/tc_l2/src/main/scala/core/id/IDU.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.InstConfig
-
 class IDU extends Module with InstConfig {
   val io = IO(new Bundle {
     val globalEn = Input(Bool())
diff --git a/rtl/tc_l2/src/main/scala/core/id/ISADecoder.scala b/rtl/tc_l2/src/main/scala/core/id/ISADecoder.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.InstConfig
-
 object ISADecoder {
   // according to the The RISC-V Instruction Set Manual Volume I: Unprivileged ISA
   // Document Version: 20191213
diff --git a/rtl/tc_l2/src/main/scala/core/id/ImmExten.scala b/rtl/tc_l2/src/main/scala/core/id/ImmExten.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.InstConfig
-
 class ImmExten extends Module with InstConfig {
   val io = IO(new Bundle {
     val inst     = Input(UInt(InstLen.W))
diff --git a/rtl/tc_l2/src/main/scala/core/id/RegFile.scala b/rtl/tc_l2/src/main/scala/core/id/RegFile.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.InstConfig
-
 class RegFile extends InstConfig {
   // public registers
   val gpr = RegInit(VecInit(Seq.fill(RegfileNum)(0.U(XLen.W))))
diff --git a/rtl/tc_l2/src/main/scala/core/if/BPU.scala b/rtl/tc_l2/src/main/scala/core/if/BPU.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.{ConstVal, InstConfig}
-
 class BPU extends Module with InstConfig {
   // 2BP 2BC
   // Two-level adaptive predictor
diff --git a/rtl/tc_l2/src/main/scala/core/if/BTB.scala b/rtl/tc_l2/src/main/scala/core/if/BTB.scala
@@ -3,7 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.{ConstVal, InstConfig}
 
 class BTBLine extends Bundle {
   val pc   = UInt(ConstVal.AddrLen.W)
diff --git a/rtl/tc_l2/src/main/scala/core/if/Cache.scala b/rtl/tc_l2/src/main/scala/core/if/Cache.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.InstConfig
-
 class CacheReqIO extends Bundle with InstConfig {
   val addr = UInt(XLen.W)
   val data = UInt(XLen.W) // for write
diff --git a/rtl/tc_l2/src/main/scala/core/if/GHR.scala b/rtl/tc_l2/src/main/scala/core/if/GHR.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.{ConstVal, InstConfig}
-
 class GHR extends Module with InstConfig {
   val io = IO(new Bundle {
     val branch = Input(Bool())
diff --git a/rtl/tc_l2/src/main/scala/core/if/IFU.scala b/rtl/tc_l2/src/main/scala/core/if/IFU.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.InstConfig
-
 class IFU extends Module with InstConfig {
   val io = IO(new Bundle {
     val globalEn   = Input(Bool())
diff --git a/rtl/tc_l2/src/main/scala/core/if/PHT.scala b/rtl/tc_l2/src/main/scala/core/if/PHT.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.InstConfig
-
 class PHT extends Module with InstConfig {
   val io = IO(new Bundle {
     // branch info (from idu)
diff --git a/rtl/tc_l2/src/main/scala/core/ma/CLINT.scala b/rtl/tc_l2/src/main/scala/core/ma/CLINT.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.InstConfig
-
 class CLINT extends Module with InstConfig {
   val io = IO(new Bundle {
     val valid  = Input(Bool())
diff --git a/rtl/tc_l2/src/main/scala/core/ma/LSU.scala b/rtl/tc_l2/src/main/scala/core/ma/LSU.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.InstConfig
-
 class LSU extends Module with InstConfig {
   val io = IO(new Bundle {
     val valid  = Input(Bool())
diff --git a/rtl/tc_l2/src/main/scala/core/wb/WBU.scala b/rtl/tc_l2/src/main/scala/core/wb/WBU.scala
@@ -5,8 +5,6 @@ import chisel3.util._
 
 import difftest._
 
-import treecorel2.common.InstConfig
-
 class WBU extends Module with InstConfig {
   val io = IO(new Bundle {
     val globalEn = Input(Bool())
diff --git a/rtl/tc_l2/src/main/scala/port/BRANCH.scala b/rtl/tc_l2/src/main/scala/port/BRANCH.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.{ConstVal, InstConfig}
-
 class BRANCHIO extends Bundle {
   val branch = Output(Bool()) // prev inst is a b/j
   val jump   = Output(Bool()) // is 'jal' or 'jalr'
diff --git a/rtl/tc_l2/src/main/scala/port/IF2IDIO.scala b/rtl/tc_l2/src/main/scala/port/IF2IDIO.scala
@@ -3,8 +3,6 @@ package treecorel2
 import chisel3._
 import chisel3.util._
 
-import treecorel2.common.InstConfig
-
 class IF2IDIO extends Bundle {
   val valid     = Output(Bool())
   val inst      = Output(UInt(32.W))
diff --git a/rtl/tc_l2/src/main/scala/port/LSIO.scala b/rtl/tc_l2/src/main/scala/port/LSIO.scala
@@ -15,4 +15,4 @@ class SDIO extends Bundle {
   val addr = Output(UInt(64.W))
   val data = Output(UInt(64.W))
   val mask = Output(UInt(8.W))
-}
+}
diff --git a/rtl/tc_l2/src/main/scala/top/TopMain.scala b/rtl/tc_l2/src/main/scala/top/TopMain.scala
@@ -1,7 +1,8 @@
 package top
 
 import sim._
-import treecorel2.common.InstConfig
+
+import treecorel2.InstConfig
 
 object TopMain extends App with InstConfig {
   if (!SoCEna) {

Original file line number	Diff line number	Diff line change
`@@ -1,4 +1,4 @@`
`1`		`-package treecorel2.common`
	`1`	`+package treecorel2`
`2`	`2`
`3`	`3`	`import chisel3._`
`4`	`4`	`import chisel3.util._`