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maksyukimaksyuki
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Merge branch 'tc-l2' into dev
2 parents 38ca547 + e1e5773 commit d148060

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16 files changed

+239
-135
lines changed

16 files changed

+239
-135
lines changed

‎rtl/tc_l2/src/main/scala/common/ConstVal.scala‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -31,8 +31,8 @@ object ConstVal {
3131
// branch prediction
3232
val GHRLen = 5
3333
val PHTSize = 1 << GHRLen
34-
val BTBIdxLen = 6
35-
val BTBPcLen = AddrLen - BTBIdxLen - AddrAlignLen
36-
val BTBTgtLen = AddrLen - AddrAlignLen
34+
val BTBIdxLen = 5
35+
val BTBPcLen = AddrLen - BTBIdxLen
36+
val BTBTgtLen = AddrLen
3737
val BTBSize = 1 << BTBIdxLen
3838
}

‎rtl/tc_l2/src/main/scala/core/TreeCoreL2.scala‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,9 @@ class TreeCoreL2 extends Module {
3939
exu.io.stall <> idu.io.stall
4040
exu.io.stall <> ifu.io.stall
4141

42+
// branch prediction
43+
ifu.io.branchInfo <> exu.io.branchInfo
44+
4245
// bypass
4346
idu.io.wbdata <> wbu.io.wbdata
4447
exu.io.bypassMem <> mau.io.bypassMem

‎rtl/tc_l2/src/main/scala/core/exec/ACU.scala‎

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,42 @@
1+
package treecorel2
2+
3+
import chisel3._
4+
import chisel3.util._
5+
6+
import treecorel2.common.ConstVal
7+
8+
class AGU extends Module {
9+
val io = IO(new Bundle {
10+
val isa = Input(new ISAIO)
11+
val src1 = Input(UInt(ConstVal.AddrLen.W))
12+
val src2 = Input(UInt(ConstVal.AddrLen.W))
13+
val valid = Output(Bool())
14+
val busy = Output(Bool())
15+
val res = Output(UInt(ConstVal.AddrLen.W))
16+
})
17+
18+
// cordic or gcd
19+
// https://zhuanlan.zhihu.com/p/304477416
20+
// https://zhuanlan.zhihu.com/p/365058686
21+
protected val val1Reg = RegInit(0.U(64.W))
22+
protected val val2Reg = RegInit(0.U(64.W))
23+
protected val busyReg = RegInit(false.B)
24+
protected val gcdVis = io.isa.GCD
25+
26+
when(gcdVis && !busyReg) {
27+
val1Reg := io.src1
28+
val2Reg := io.src2
29+
busyReg := true.B
30+
}.elsewhen(busyReg) {
31+
when(val1Reg > val2Reg) {
32+
val1Reg := val1Reg - val2Reg
33+
}.otherwise {
34+
val2Reg := val2Reg - val1Reg
35+
}
36+
}
37+
38+
when(val2Reg === 0.U(64.W)) { busyReg := false.B }
39+
io.valid := (val2Reg === 0.U(64.W) && busyReg)
40+
io.busy := busyReg
41+
io.res := val1Reg
42+
}

‎rtl/tc_l2/src/main/scala/core/exec/BEU.scala‎

Lines changed: 26 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -3,24 +3,29 @@ package treecorel2
33
import chisel3._
44
import chisel3.util._
55

6+
import treecorel2.common.ConstVal
7+
68
class BEU extends Module {
79
val io = IO(new Bundle {
8-
val isa = Input(new ISAIO)
9-
val imm = Input(new IMMIO)
10-
val src1 = Input(UInt(64.W))
11-
val src2 = Input(UInt(64.W))
12-
val pc = Input(UInt(64.W))
13-
val branch = Output(Bool())
14-
val tgt = Output(UInt(64.W))
10+
val isa = Input(new ISAIO)
11+
val imm = Input(new IMMIO)
12+
val src1 = Input(UInt(64.W))
13+
val src2 = Input(UInt(64.W))
14+
val pc = Input(UInt(64.W))
15+
val branIdx = Input(UInt(ConstVal.GHRLen.W))
16+
val branchInfo = new BRANCHIO
17+
val branch = Output(Bool())
18+
val tgt = Output(UInt(64.W))
1519
})
1620

17-
protected val beq = io.isa.BEQ && (io.src1 === io.src2)
18-
protected val bne = io.isa.BNE && (io.src1 =/= io.src2)
19-
protected val bgeu = io.isa.BGEU && (io.src1 >= io.src2)
20-
protected val bltu = io.isa.BLTU && (io.src1 < io.src2)
21-
protected val bge = io.isa.BGE && (io.src1.asSInt >= io.src2.asSInt)
22-
protected val blt = io.isa.BLT && (io.src1.asSInt < io.src2.asSInt)
23-
protected val b = beq | bne | bgeu | bltu | bge | blt
21+
protected val beq = io.isa.BEQ && (io.src1 === io.src2)
22+
protected val bne = io.isa.BNE && (io.src1 =/= io.src2)
23+
protected val bgeu = io.isa.BGEU && (io.src1 >= io.src2)
24+
protected val bltu = io.isa.BLTU && (io.src1 < io.src2)
25+
protected val bge = io.isa.BGE && (io.src1.asSInt >= io.src2.asSInt)
26+
protected val blt = io.isa.BLT && (io.src1.asSInt < io.src2.asSInt)
27+
protected val b = beq | bne | bgeu | bltu | bge | blt
28+
protected val bInst = io.isa.BEQ || io.isa.BNE || io.isa.BGEU || io.isa.BLTU || io.isa.BGE || io.isa.BLT || io.isa.JAL || io.isa.JALR
2429

2530
protected val jal = io.isa.JAL
2631
protected val jalr = io.isa.JALR
@@ -38,4 +43,11 @@ class BEU extends Module {
3843
}.otherwise {
3944
io.tgt := b_tgt
4045
}
46+
47+
io.branchInfo.branch := bInst
48+
io.branchInfo.jump := jal || jalr
49+
io.branchInfo.taken := io.branch
50+
io.branchInfo.idx := io.branIdx
51+
io.branchInfo.pc := io.pc
52+
io.branchInfo.tgt := io.tgt
4153
}

‎rtl/tc_l2/src/main/scala/core/exec/EXU.scala‎

Lines changed: 52 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -5,26 +5,29 @@ import chisel3.util._
55

66
class EXU extends Module {
77
val io = IO(new Bundle {
8-
val globalEn = Input(Bool())
9-
val mtip = Input(Bool())
10-
val stall = Output(Bool())
11-
val id2ex = Flipped(new ID2EXIO)
12-
val bypassMem = Flipped(new WBDATAIO)
13-
val bypassWb = Flipped(new WBDATAIO)
14-
val ex2mem = new EX2MEMIO
15-
val nxtPC = new NXTPCIO
8+
val globalEn = Input(Bool())
9+
val mtip = Input(Bool())
10+
val stall = Output(Bool())
11+
val id2ex = Flipped(new ID2EXIO)
12+
val bypassMem = Flipped(new WBDATAIO)
13+
val bypassWb = Flipped(new WBDATAIO)
14+
val ex2mem = new EX2MEMIO
15+
val nxtPC = new NXTPCIO
16+
val branchInfo = new BRANCHIO
1617
})
1718

18-
protected val exReg = RegEnable(io.id2ex, WireInit(0.U.asTypeOf(new ID2EXIO())), io.globalEn)
19-
protected val valid = exReg.valid
20-
protected val inst = exReg.inst
21-
protected val pc = exReg.pc
22-
protected val isa = exReg.isa
23-
protected val imm = exReg.imm
24-
protected val wen = exReg.wen
25-
protected val rs1 = exReg.inst(19, 15)
26-
protected val rs2 = exReg.inst(24, 20)
27-
protected val wdest = exReg.wdest
19+
protected val exReg = RegEnable(io.id2ex, WireInit(0.U.asTypeOf(new ID2EXIO())), io.globalEn)
20+
protected val valid = exReg.valid
21+
protected val inst = exReg.inst
22+
protected val pc = exReg.pc
23+
protected val branIdx = exReg.branIdx
24+
protected val predTaken = exReg.predTaken
25+
protected val isa = exReg.isa
26+
protected val imm = exReg.imm
27+
protected val wen = exReg.wen
28+
protected val rs1 = exReg.inst(19, 15)
29+
protected val rs2 = exReg.inst(24, 20)
30+
protected val wdest = exReg.wdest
2831

2932
protected val bypassMemSrc1En = io.bypassMem.wen && (rs1 === io.bypassMem.wdest) && (rs1 =/= 0.U)
3033
protected val bypassMemSrc2En = io.bypassMem.wen && (rs2 === io.bypassMem.wdest) && (rs2 =/= 0.U)
@@ -40,18 +43,26 @@ class EXU extends Module {
4043
alu.io.src2 := src2
4144
protected val aluRes = alu.io.res
4245

43-
protected val mdu = Module(new MDU)
44-
mdu.io.isa := isa
45-
mdu.io.src1 := src1
46-
mdu.io.src2 := src2
47-
protected val mduRes = mdu.io.res
46+
// protected val mdu = Module(new MDU)
47+
// mdu.io.isa := isa
48+
// mdu.io.src1 := src1
49+
// mdu.io.src2 := src2
50+
// protected val mduRes = mdu.io.res
51+
52+
// protected val agu = Module(new AGU)
53+
// agu.io.isa := isa
54+
// agu.io.src1 := src1
55+
// agu.io.src2 := src2
56+
// protected val aguRes = agu.io.res
4857

4958
protected val beu = Module(new BEU)
50-
beu.io.isa := isa
51-
beu.io.imm := imm
52-
beu.io.src1 := src1
53-
beu.io.src2 := src2
54-
beu.io.pc := pc
59+
beu.io.isa := isa
60+
beu.io.imm := imm
61+
beu.io.src1 := src1
62+
beu.io.src2 := src2
63+
beu.io.pc := pc
64+
beu.io.branIdx := branIdx
65+
beu.io.branchInfo <> io.branchInfo
5566
protected val branch = beu.io.branch
5667
protected val tgt = beu.io.tgt
5768

@@ -68,25 +79,29 @@ class EXU extends Module {
6879
protected val timeIntrEn = csrReg.io.timeIntrEn
6980
protected val ecallEn = csrReg.io.ecallEn
7081

71-
io.nxtPC.trap := valid && (timeIntrEn || ecallEn)
72-
io.nxtPC.mtvec := csrReg.io.csrState.mtvec
73-
io.nxtPC.mret := valid && isa.MRET
74-
io.nxtPC.mepc := csrReg.io.csrState.mepc
75-
io.nxtPC.branch := valid && branch
76-
io.nxtPC.tgt := tgt
77-
78-
io.stall := valid && (branch || timeIntrEn || ecallEn || isa.MRET)
82+
io.nxtPC.trap := valid && (timeIntrEn || ecallEn)
83+
io.nxtPC.mtvec := csrReg.io.csrState.mtvec
84+
io.nxtPC.mret := valid && isa.MRET
85+
io.nxtPC.mepc := csrReg.io.csrState.mepc
86+
// (pred, fact)--->(NT, T) or (T, NT)
87+
protected val predNTfactT = branch && !predTaken
88+
protected val predTfactNT = !branch && predTaken
89+
io.nxtPC.branch := valid && (predNTfactT || predTfactNT)
90+
io.nxtPC.tgt := Mux(valid && predNTfactT, tgt, Mux(valid && predTfactNT, pc + 4.U, 0.U(64.W)))
91+
io.stall := valid && (io.nxtPC.branch || timeIntrEn || ecallEn || isa.MRET)
7992

8093
io.ex2mem.valid := Mux(timeIntrEn, false.B, valid)
8194
io.ex2mem.inst := inst
8295
io.ex2mem.pc := pc
96+
io.ex2mem.branIdx := branIdx
97+
io.ex2mem.predTaken := predTaken
8398
io.ex2mem.isa := isa
8499
io.ex2mem.src1 := src1
85100
io.ex2mem.src2 := src2
86101
io.ex2mem.imm := imm
87102
io.ex2mem.wen := wen
88103
io.ex2mem.wdest := wdest
89-
io.ex2mem.aluRes := aluRes | mduRes
104+
io.ex2mem.aluRes := aluRes
90105
io.ex2mem.branch := branch
91106
io.ex2mem.tgt := tgt
92107
io.ex2mem.link := link

‎rtl/tc_l2/src/main/scala/core/exec/MDU.scala‎

Lines changed: 26 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -8,34 +8,38 @@ object MDUOpType {
88
def mulh = "b0001".U
99
def mulhsu = "b0010".U
1010
def mulhu = "b0011".U
11-
def div = "b0100".U
12-
def divu = "b0101".U
13-
def rem = "b0110".U
14-
def remu = "b0111".U
11+
def mulw = "b0100".U
1512

16-
def mulw = "b1000".U
17-
def divw = "b1100".U
18-
def divuw = "b1101".U
19-
def remw = "b1110".U
20-
def remuw = "b1111".U
13+
def div = "b1000".U
14+
def divu = "b1001".U
15+
def divuw = "b1010".U
16+
def divw = "b1011".U
17+
def rem = "b1100".U
18+
def remu = "b1101".U
19+
def remuw = "b1110".U
20+
def remw = "b1111".U
2121

22+
def nop = "b1001".U
23+
24+
def isMul(op: UInt) = !op(3)
25+
def isDiv(op: UInt) = op(3) && !(!op(2) && !op(1) && op(0))
2226
def isLhsSign(op: UInt) = false.B
2327
def isRhsSign(op: UInt) = false.B
24-
def isDiv(op: UInt) = op(2)
25-
def isDivSign(op: UInt) = isDiv(op) && !op(0)
28+
def isDivSign(op: UInt) = false.B
2629
def isHiRem(op: UInt) = false.B
27-
def isW(op: UInt) = op(3)
30+
def isW(op: UInt) = false.B
2831
}
2932

3033
class MDU extends Module {
3134
val io = IO(new Bundle {
32-
val isa = Input(new ISAIO)
33-
val src1 = Input(UInt(64.W))
34-
val src2 = Input(UInt(64.W))
35-
val res = Output(UInt(64.W))
35+
val isa = Input(new ISAIO)
36+
val src1 = Input(UInt(64.W))
37+
val src2 = Input(UInt(64.W))
38+
val res = Output(UInt(64.W))
39+
val valid = Output(Bool())
3640
})
3741

38-
protected val mduOp = RegInit(0.U(4.W))
42+
protected val mduOp = RegInit(MDUOpType.nop)
3943
when(io.isa.MUL) {
4044
mduOp := MDUOpType.mul
4145
}.elsewhen(io.isa.MULH) {
@@ -66,6 +70,7 @@ class MDU extends Module {
6670

6771
protected val isLhsSign = MDUOpType.isLhsSign(mduOp)
6872
protected val isRhsSign = MDUOpType.isRhsSign(mduOp)
73+
protected val isMul = MDUOpType.isMul(mduOp)
6974
protected val isDiv = MDUOpType.isDiv(mduOp)
7075
protected val isHiRem = MDUOpType.isHiRem(mduOp)
7176

@@ -76,10 +81,10 @@ class MDU extends Module {
7681
protected val isAnsNeg = isSrc1Neg ^ isSrc2Neg
7782
protected val src1 = Mux(isSrc1Neg, -io.src1, io.src1)
7883
protected val src2 = Mux(isSrc2Neg, -io.src2, io.src2)
84+
multiplier.io.en := isMul
85+
multiplier.io.flush := false.B
7986
multiplier.io.src1 := src1
8087
multiplier.io.src2 := src2
81-
multiplier.io.en := false.B
82-
multiplier.io.flush := false.B
8388

8489
protected val mulRes = Mux(isAnsNeg, -multiplier.io.res, multiplier.io.res)
8590

@@ -98,7 +103,6 @@ class MDU extends Module {
98103
divider.io.divident := src1
99104
divider.io.divisor := src2
100105

101-
// io.valid := Mux(!isDiv, multiplier.io.done, Mux(isDiv, divider.io.done, true.B))
102-
// io.res := Mux(!isDiv, mulRes, Mux(isDiv, divRes, 0.U))
103-
io.res := 0.U
106+
io.valid := Mux(isMul, multiplier.io.done, Mux(isDiv, divider.io.done, true.B))
107+
io.res := Mux(isMul, mulRes, Mux(isDiv, divRes, 0.U(64.W)))
104108
}

‎rtl/tc_l2/src/main/scala/core/id/IDU.scala‎

Lines changed: 18 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -13,10 +13,12 @@ class IDU extends Module {
1313
val gpr = Output(Vec(32, UInt(64.W)))
1414
})
1515

16-
protected val idReg = RegEnable(io.if2id, WireInit(0.U.asTypeOf(new IF2IDIO())), io.globalEn)
17-
protected val valid = idReg.valid
18-
protected val inst = idReg.inst
19-
protected val pc = idReg.pc
16+
protected val idReg = RegEnable(io.if2id, WireInit(0.U.asTypeOf(new IF2IDIO())), io.globalEn)
17+
protected val valid = idReg.valid
18+
protected val inst = idReg.inst
19+
protected val pc = idReg.pc
20+
protected val branIdx = idReg.branIdx
21+
protected val predTaken = idReg.predTaken
2022

2123
protected val rs1 = inst(19, 15)
2224
protected val rs2 = inst(24, 20)
@@ -38,14 +40,16 @@ class IDU extends Module {
3840
regfile.write(io.wbdata.wen, io.wbdata.wdest, io.wbdata.data)
3941
}
4042

41-
io.id2ex.valid := Mux(io.stall, false.B, valid)
42-
io.id2ex.inst := inst
43-
io.id2ex.pc := pc
44-
io.id2ex.isa := isa
45-
io.id2ex.src1 := src1
46-
io.id2ex.src2 := src2
47-
io.id2ex.imm := imm
48-
io.id2ex.wen := wen
49-
io.id2ex.wdest := wdest
50-
io.gpr := regfile.gpr
43+
io.id2ex.valid := Mux(io.stall, false.B, valid)
44+
io.id2ex.inst := inst
45+
io.id2ex.pc := pc
46+
io.id2ex.branIdx := branIdx
47+
io.id2ex.predTaken := predTaken
48+
io.id2ex.isa := isa
49+
io.id2ex.src1 := src1
50+
io.id2ex.src2 := src2
51+
io.id2ex.imm := imm
52+
io.id2ex.wen := wen
53+
io.id2ex.wdest := wdest
54+
io.gpr := regfile.gpr
5155
}

‎rtl/tc_l2/src/main/scala/core/id/ISADecoder.scala‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -88,6 +88,7 @@ class ISADecoder extends Module {
8888
io.isa.REMU := (io.inst === BitPat("b0000001_?????_?????_111_?????_0110011"))
8989
io.isa.REMUW := (io.inst === BitPat("b0000001_?????_?????_111_?????_0111011"))
9090
io.isa.REMW := (io.inst === BitPat("b0000001_?????_?????_110_?????_0111011"))
91+
io.isa.GCD := (io.inst === BitPat("b0000000_?????_?????_000_?????_0001000"))
9192

9293
protected val arith = io.isa.ADD || io.isa.ADDW || io.isa.ADDI || io.isa.ADDIW || io.isa.SUB || io.isa.SUBW || io.isa.LUI || io.isa.AUIPC
9394
protected val logc = io.isa.XOR || io.isa.XORI || io.isa.OR || io.isa.ORI || io.isa.AND || io.isa.ANDI
@@ -101,10 +102,11 @@ class ISADecoder extends Module {
101102
protected val env = io.isa.ECALL || io.isa.EBREAK
102103
protected val csr = io.isa.CSRRW || io.isa.CSRRS || io.isa.CSRRC || io.isa.CSRRWI || io.isa.CSRRSI || io.isa.CSRRCI
103104
protected val priv = io.isa.MRET || io.isa.SRET || io.isa.WFI || io.isa.SFENCE_VMA
105+
protected val custom = io.isa.GCD
104106

105107
protected val immExten = Module(new ImmExten)
106108
immExten.io.inst := io.inst
107109
io.imm := immExten.io.imm
108110
io.csr := csr
109-
io.wen := arith || logc || shift || comp || link || load || csr
111+
io.wen := arith || logc || shift || comp || link || load || csr || custom
110112
}

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