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rtl/tc_l2/src/main/scala/core/if Expand file tree Collapse file tree 2 files changed +6
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lines changed Original file line number Diff line number Diff line change @@ -40,9 +40,9 @@ class BTB extends Module {
4040 }
4141
4242 // signals about BTB lookup
43- val lookupIdx = io.lookupPc(ConstVal .BTBIdxLen - 1 , 0 )
44- val lookupPcSel = io.lookupPc
45- val btbHit = valids(lookupIdx) && lines(lookupIdx).pc === lookupPcSel
43+ protected val lookupIdx = io.lookupPc(ConstVal .BTBIdxLen - 1 , 0 )
44+ protected val lookupPcSel = io.lookupPc
45+ protected val btbHit = valids(lookupIdx) && lines(lookupIdx).pc === lookupPcSel
4646
4747 // BTB lookup
4848 io.lookupBranch := btbHit
Original file line number Diff line number Diff line change @@ -12,11 +12,11 @@ class GHR extends Module {
1212 val idx = Output (UInt (ConstVal .GHRLen .W ))
1313 })
1414
15- protected val ghr = Reg (UInt (ConstVal .GHRLen .W ))
15+ protected val shiftReg = Reg (UInt (ConstVal .GHRLen .W ))
1616
1717 when(io.branch) {
18- ghr := Cat (ghr (ConstVal .GHRLen - 2 , 0 ), io.taken)
18+ shiftReg := Cat (shiftReg (ConstVal .GHRLen - 2 , 0 ), io.taken)
1919 }
2020
21- io.idx := ghr
21+ io.idx := shiftReg
2222}
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