[pull] master from buildroot:master

.checkpackageignore

@@ -1068,7 +1068,6 @@ support/libtool/buildroot-libtool-v2.4.4.patch lib_patch.ApplyOrder lib_patch.Up
 support/libtool/buildroot-libtool-v2.4.patch lib_patch.ApplyOrder lib_patch.Sob lib_patch.Upstream
 support/misc/relocate-sdk.sh Shellcheck
 support/scripts/apply-patches.sh Shellcheck
-support/scripts/br2-external Shellcheck
 support/scripts/check-bin-arch Shellcheck
 support/scripts/check-host-rpath Shellcheck
 support/scripts/expunge-gconv-modules Shellcheck

arch/Config.in.arm

@@ -498,6 +498,12 @@ config BR2_tsv110
 	select BR2_ARCH_NEEDS_GCC_AT_LEAST_9
 
 comment "armv8.4a cores"
+config BR2_neoverse_v1
+	bool "neoverse-V1 (aka zeus)"
+	depends on BR2_ARCH_IS_64
+	select BR2_ARM_CPU_HAS_FP_ARMV8
+	select BR2_ARM_CPU_ARMV8A
+	select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
 config BR2_saphira
 	bool "saphira"
 	depends on BR2_ARCH_IS_64
@@ -518,6 +524,12 @@ config BR2_neoverse_n2
 	select BR2_ARM_CPU_HAS_FP_ARMV8
 	select BR2_ARM_CPU_ARMV9A
 	select BR2_ARCH_NEEDS_GCC_AT_LEAST_11
+config BR2_neoverse_v2
+	bool "neoverse-V2 (aka demeter)"
+	depends on BR2_ARCH_IS_64
+	select BR2_ARM_CPU_HAS_FP_ARMV8
+	select BR2_ARM_CPU_ARMV9A
+	select BR2_ARCH_NEEDS_GCC_AT_LEAST_13
 
 comment "armv9.2a cores"
 config BR2_cortex_a720
@@ -526,6 +538,18 @@ config BR2_cortex_a720
 	select BR2_ARM_CPU_HAS_FP_ARMV8
 	select BR2_ARM_CPU_ARMV9A
 	select BR2_ARCH_NEEDS_GCC_AT_LEAST_14
+config BR2_neoverse_v3
+	bool "neoverse-V3 (aka poseidon)"
+	depends on BR2_ARCH_IS_64
+	select BR2_ARM_CPU_HAS_FP_ARMV8
+	select BR2_ARM_CPU_ARMV9A
+	select BR2_ARCH_NEEDS_GCC_AT_LEAST_15
+config BR2_neoverse_v3ae
+	bool "neoverse-V3AE (aka poseidon)"
+	depends on BR2_ARCH_IS_64
+	select BR2_ARM_CPU_HAS_FP_ARMV8
+	select BR2_ARM_CPU_ARMV9A
+	select BR2_ARCH_NEEDS_GCC_AT_LEAST_15
 endchoice
 
 config BR2_ARM_ENABLE_NEON
@@ -918,12 +942,16 @@ config BR2_GCC_TARGET_CPU
 	default "neoverse-n1"	if BR2_neoverse_n1
 	default "tsv110"	if BR2_tsv110
 	# armv8.4a
+	default "neoverse-v1"   if BR2_neoverse_v1
 	default "saphira"	if BR2_saphira
 	# armv9.0a
 	default "cortex-a710"	if BR2_cortex_a710
 	default "neoverse-n2"	if BR2_neoverse_n2
+	default "neoverse-v2"	if BR2_neoverse_v2
 	# armv9.2a
 	default "cortex-a720"	if BR2_cortex_a720
+	default "neoverse-v3"	if BR2_neoverse_v3
+	default "neoverse-v3ae"	if BR2_neoverse_v3ae
 
 config BR2_GCC_TARGET_ABI
 	default "aapcs-linux"	if BR2_arm || BR2_armeb

board/stmicroelectronics/common/stm32mp1xx/patches/uboot/001-ARM-dts-stm32-Add-SCMI-clocks-in-rcc-node-for-stm32m.patch

@@ -0,0 +1,59 @@
+From ebfc6864f27c7170422db0c8c3d934f23a8a83b7 Mon Sep 17 00:00:00 2001
+From: Patrice Chotard <patrice.chotard@foss.st.com>
+Date: Fri, 16 Jan 2026 19:57:26 +0100
+Subject: [PATCH] ARM: dts: stm32: Add SCMI clocks in rcc node for
+ stm32mp131.dtsi
+
+Add SCMI clocks. These clocks are used as parent clocks and are
+referenced by their rcc's node position in clk-stm32mp13.c
+
+Fixes: fdb1bffe2827 ("clk: scmi: Postpone clock name resolution")
+Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
+Upstream: https://source.denx.de/u-boot/u-boot/-/commit/7795c5ec6a608a104cf41331cbd387d39f7f6f49
+Signed-off-by: Thomas Richard <thomas.richard@bootlin.com>
+---
+ arch/arm/dts/stm32mp13-u-boot.dtsi | 27 +++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+diff --git a/arch/arm/dts/stm32mp13-u-boot.dtsi b/arch/arm/dts/stm32mp13-u-boot.dtsi
+index ad63d5027b2..623c796cc79 100644
+--- a/arch/arm/dts/stm32mp13-u-boot.dtsi
++++ b/arch/arm/dts/stm32mp13-u-boot.dtsi
+@@ -186,6 +186,33 @@
+ };
+
+ &rcc {
++	clocks = <&scmi_clk CK_SCMI_HSE>,
++		 <&scmi_clk CK_SCMI_HSI>,
++		 <&scmi_clk CK_SCMI_CSI>,
++		 <&scmi_clk CK_SCMI_LSE>,
++		 <&scmi_clk CK_SCMI_LSI>,
++		 <&scmi_clk CK_SCMI_HSE_DIV2>,
++		 <&scmi_clk CK_SCMI_PLL2_Q>,
++		 <&scmi_clk CK_SCMI_PLL2_R>,
++		 <&scmi_clk CK_SCMI_PLL3_P>,
++		 <&scmi_clk CK_SCMI_PLL3_Q>,
++		 <&scmi_clk CK_SCMI_PLL3_R>,
++		 <&scmi_clk CK_SCMI_PLL4_P>,
++		 <&scmi_clk CK_SCMI_PLL4_Q>,
++		 <&scmi_clk CK_SCMI_PLL4_R>,
++		 <&scmi_clk CK_SCMI_MPU>,
++		 <&scmi_clk CK_SCMI_AXI>,
++		 <&scmi_clk CK_SCMI_MLAHB>,
++		 <&scmi_clk CK_SCMI_CKPER>,
++		 <&scmi_clk CK_SCMI_PCLK1>,
++		 <&scmi_clk CK_SCMI_PCLK2>,
++		 <&scmi_clk CK_SCMI_PCLK3>,
++		 <&scmi_clk CK_SCMI_PCLK4>,
++		 <&scmi_clk CK_SCMI_PCLK5>,
++		 <&scmi_clk CK_SCMI_PCLK6>,
++		 <&scmi_clk CK_SCMI_CKTIMG1>,
++		 <&scmi_clk CK_SCMI_CKTIMG2>,
++		 <&scmi_clk CK_SCMI_CKTIMG3>;
+ 	bootph-all;
+ };
+
+-- 
+2.51.0
+