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@lt lt commented Nov 2, 2025

I've been working on a port of perfect6502/visual6502 to Go and have made a couple of optimisations in my own code that you might like for yours.

transistor_on mirrors nodes_value[gate] for each transistor. By making c1c2 reference the gate node rather than the transistor index, a level of indirection can be avoided.

Since the transistor netlist entries in this implementation are ordered by gate node_block ends up being node_block[n] = n, so this can be optimised out. This does mean if you want to use this simulator with any other netlist (i.e. z80, 8080) those netlists will also need to be sorted before use.

Lastly nodes_gates is now only used in initialisation and can be removed from the state.

Testing using make benchmark I was able to observe a 3-4% performance gain.

lt added 2 commits November 2, 2025 22:22
* transistor_on is a fanout of the gate state, so we can avoid a level
  of indirection by checking the gate directly.
* Since the transistor netlist is ordered by gate node_block ends up
  being `node_block[n] = n`, so this can be optimised out.
* nodes_gates is now only used in initialisation and can be removed from
  the state.
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