mvg-internship
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lorina
lorina PublicForked from hriener/lorina
C++ parsing library for simple formats used in logic synthesis and formal verification
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vtr-fpga-arch
vtr-fpga-arch PublicForked from verilog-to-routing/vtr-verilog-to-routing
Fork of Verilog to Routing -- Open Source CAD Flow for FPGA Research
C++ 1
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OpenLane
OpenLane PublicForked from The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
Python
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- OpenLane Public Forked from The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
mvg-internship/OpenLane’s past year of commit activity - basicviz Public
mvg-internship/basicviz’s past year of commit activity - lorina Public Forked from hriener/lorina
C++ parsing library for simple formats used in logic synthesis and formal verification
mvg-internship/lorina’s past year of commit activity - utopia-eda Public
mvg-internship/utopia-eda’s past year of commit activity - vtr-fpga-arch Public Forked from verilog-to-routing/vtr-verilog-to-routing
Fork of Verilog to Routing -- Open Source CAD Flow for FPGA Research
mvg-internship/vtr-fpga-arch’s past year of commit activity
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