UART Interface for FPGA

Introduction

UART, or Universal Asynchronous Receiver-Transmitter, is one of the most commonly used device-to-device communication protocols. It is a fundamental component in many electronic systems that require reliable, low-speed serial communication without the complexity of managing a clock signal.

learn more about UART in this article by Analog Devices.

Purpose

This project provides a standard UART interface for FPGA devices. It is designed to be easily integrated into computational projects and can serve as a reference for more complex UART implementations. Note that while the board used in this project has native UART capabilities, this implementation is intended for interfacing with any generic FPGA device.

• Protocol Parameters: 8 data bits, no parity, 1 stop bit (8N1 configuration).
• Clock Frequency & Baud Rate: 125 MHz clock frequency and 115200 bit/s baud rate, which can be parameterized within the fpga_uart_top module.
• Echo Functionality: The uart_echo module transmits received data back to the sender. Custom logic can be implemented to process the data.
• Additional Features: The design includes a physical reset button along with LED indicators for reset, RX error, TX activity, and RX activity.

Programming a Device

The provided IP (ip/clk_wiz_0.xci) and constraints file (constraints/arty-z7-20.xdc) are compatible with environment described below and may require modification depending on your environment. However, the SystemVerilog source files in the rtl directory are developed to be synthesiable on generic FPGA devices.

Environment

Hardware

• Arty-Z7-20 Development Board by Digilent
• CP2102 USB-to-UART Bridge Controller by Silicon Labs
• Generic 0.1‑inch male connectors

Software

• Ubuntu 22.04.5 LTS
• Vivado 2024.2
• minicom 2.8

Steps

1. Create a New Vivado Project:

   • Launch Vivado with sudo privileges¹.
   • Add the following source files:
     • rtl/fpga_uart_top.sv
     • rtl/uart_echo.sv
     • rtl/uart_rx.sv
     • rtl/uart_tx.sv
     • rtl/retriggerable_one_shot.sv
     • rtl/synchronous_debouncer.sv
     • ip/clk_wiz_0.xci
   • Add the constraints file: constraints/arty-z7-20.xdc.

2. Generate the Bitstream:

   • Run synthesis and implementation.
   • Generate the bitstream, ensuring that both processes complete successfully.

3. Connect the Hardware:

   • Connect the Arty-Z7-20 to your computer via micro-USB.
   • Connect the board to the CP2102 USB-to-UART Bridge Controller as indicated in Figure 1.

Figure 1. Pmod Port Diagram. Connect the CP2102 TX to Pin 9 and RX to Pin 10.

5. Program the Device:
   • Use Vivado’s Hardware Manager to program the device.

Interfacing with the FPGA

WIth the setup connected, monitor the tty kernel log to locate the USB-to-serial adapter:

sudo dmesg | grep tty

In this case, the converter is located at /dev/ttyUSB0:

usb 1-2: cp210x converter now attached to ttyUSB0

Run minicom with sudo privileges in setup mode:

sudo minicom -s

In the configuration menu, navigate to Serial Port Setup and set the following parameters:

• Serial Device: /dev/ttyUSB0
• Hardware Flow Control: No

Exit the configuration menu and type in the minicom terminal to transmit data to the UART chip. With the provided echo demo, the minicom terminal should display the characters you type.

Footnotes

1. Ensure Vivado is run with sudo privileges to access the USB ports. This can be done by running the following command (assuming the default installation directory):

   sudo bash -c "source /tools/Xilinx/Vivado/2024.2/settings64.sh && vivado"
   

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