Add IHP, SKY130, and GF180 PDK support and detailed parameter templates

[setup99]

1. Changes in pdk.py (The Library & File Mapping) :

For every PDK, I added a dedicated PDK_...() function that acts as a dictionary of the factory's "parts list."

** Specific Cell Names: I mapped the unique naming conventions of each factory so the compiler knows which "brick" to pick:

• IHP: Uses sg13g2_ prefix (e.g., sg13g2_filltap).

• SkyWater: Uses sky130_fd_sc_hd__ prefix (e.g., sky130_fd_sc_hd__fill_1).

• GlobalFoundries: Uses gf180mcu_fd_sc_mcu7t5v0__ prefix.

** File Path Resolution: Added logic to find the three critical files required for every chip:

• Tech LEF: The "Rulebook" for the metal layers.

• StdCell LEF: The "Shapes" of the transistors.

• Liberty (.lib): The "Timing" (how fast the signals move).

2. Changes in parameters.py (The Geometric Blueprint) :

For every PDK, I created a _PARAMETERS_TEMPLATE that defines the "rules of the road" for drawing the chip.

**Track Pitches (The Grid): I extracted the exact spacing for the metal wires from the foundry technology files:

   * IHP: 420nm / 480nm tracks.

   * SKY130: 340nm / 460nm tracks.

   * GF180: 480nm / 560nm tracks.

   * This prevents "Design Rule Violations" (DRVs) where wires are too close together.

** Power Delivery Network (PDN): We added a professional power grid for every PDK:

   * Net Names: Standardized VDD/VSS for most, and VPWR/VGND specifically for SkyWater.

   * Power Stripes: Defined which heavy metal layers (usually Metal4 and Metal5) carry the main electricity across the chip.

** Layer Constraints:

   * Set the Bottom and Top routing layers (e.g., allowing routing only from Metal2 to Metal5 for IHP to save the bottom layer for cells).

** Utilization & Margins: Set safe default "density" levels (e.g., 65% for IHP, 40% for SkyWater) so the chips aren't too crowded to wire.