ECOS Studio is an integrated, one-stop silicon design solution that democratizes access to custom silicon. It vertically integrates open-source IP libraries, a robust EDA toolchain, and accessible PDKs into a unified framework, providing an "FPGA-like" experience for ASIC design.
Our goal is to lower the barrier of chip design for researchers, engineers, and students, bridging the gap from RTL design to physical realization.
This repository is organized into four main components:
Desktop application providing an integrated development environment for chip design.
- Visual Workspace Management - Create and manage chip design projects
- Automated RTL-to-GDS Flow - One-click execution from Verilog to layout
- Integrated Tools - Yosys (synthesis), ECC-Tools (placement & routing), KLayout (visualization)
- See ecos/README.md for usage guide
- See ECOS Studio User Guide for detailed documentation
Pre-verified infrastructure for composable design, including configurable SoC templates and common peripherals.
ECOS Chip Compiler (ECC): An open-source chip design automation solution that integrates EDA tools (Yosys, ECC-Tools, KLayout) to achieve complete RTL-to-GDS design flow.
Enabling mainstream manufacturing processes.
Note: This is the initial release of ECOS Studio components. We are starting by providing these foundational open-source tools to the community. More subprojects and advanced features will be added in the future. Please stay tuned for updates!
# Setup (init submodules, PDK, and ECC environment)
make setup
# Development
make dev
# Release build (wheels + bundle + AppImage)
make build
# Launch GUI
make guimake demo-gcd # GCD example
make demo-retrosoc # retroSoC exampleFor development setup, ecc-tools builds, ecc-dreamPlace builds, wheel builds, and release build details, see ecos/README.md.
For any issues you'd like to discuss, feel free to join our WeChat community.
