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    7 repositories

    • uvm_starter

      Public
      uvm_starter is a simple template for starting uvm projects
      SystemVerilog
      •
      MIT License
      •2•11•0•0•Updated Feb 11, 2025Feb 11, 2025

    • ps2_ascii

      Public
      Verilog code for converting PS/2 keyboard serial data to ascii
      Verilog
      •
      MIT License
      •2•2•0•0•Updated Feb 7, 2025Feb 7, 2025

    • aes128

      Public
      The aes128 is a SystemVerilog implementation of the AES algorithm with 128-bit key
      SystemVerilog
      •
      MIT License
      •2•7•0•0•Updated Feb 7, 2025Feb 7, 2025

    • uvm_axi4lite

      Public
      uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
      SystemVerilog
      •
      MIT License
      •7•33•0•1•Updated Feb 7, 2025Feb 7, 2025

    • axi4lite_gpio

      Public
      General purpose IO port with AXI4-Lite interface
      SystemVerilog
      •
      MIT License
      •3•10•0•0•Updated Feb 7, 2025Feb 7, 2025

    • uvm_apb

      Public
      uvm_apb is a uvm package for modeling and verifying APB (Advanced Periperal Bus) protocol
      SystemVerilog
      •
      MIT License
      •4•21•0•0•Updated Feb 7, 2025Feb 7, 2025

    • uvm_axi

      Public
      uvm_axi is a uvm package for modeling and verifying AXI protocol
      SystemVerilog
      •
      MIT License
      •6•21•0•0•Updated Feb 7, 2025Feb 7, 2025
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