Refactor EMC initialization code#15
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It will be used in const data definition later on. Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
This patch is the first step to unify SDRAM memory controller code for jz4740/4725b/4755. A320 is known to use pair of Winbond WB9812G6IH-6: 166MHz grade 16Mb chips used in parallel to get 32-bit width data bus, of course it may have other compatible chips. RS90 has 2 revisions: V2.1 133MHz grade Samsung K4S561632H-UC75 (may be others as well) V3.0 166MHz grade unknown for me chip, so Hynix HY57V281620FTP-6 taken as a reference because it mentioned in the code a few times. Both options are single chip, 16-bit data bus width, 32Mb capacity. Note pcercuei#1: samsung chip timings were taken from old code instead of datasheet because current controller code has a bad precision of converting time to clock cycles. Note pcercuei#2: SDRAM_TRWL was renamed to SDRAM_TWR and represented in clock cycles instead of time, because all datasheets mention this parameter in clock cycles. Moreover now it set to 2 as per datatasheets, while old 7ns has been converted to 1 clock cycle. I have no idea how it affects performance/overclocking then. Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
This patch is the second step to unify SDRAM memory controller code for jz4740/4725b/4755. SDRAM init routine now unified for all these SoCs, get mem capacity too. Note pcercuei#1: Samsung chip timings returned to values from datasheet, since current init routine transforms time to clocks more precisely. Note pcercuei#2: resulting binary size remains the same. Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
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for JZ4740 and jz4725b, for easier applying jz4755 in the near future.
The SDRAM parameters were heavily revised but not tested on a real hardware.
Thankfully it might be done easily without re-flashing internal storage - jzboot supports that kind of binaries to load.
Occasionally, the resulting binaries remains the same size.