Single_Cycle_CPU

A simple Single Cycle CPU for MIPS worked on Nexys3 FPGA board. Project for Course 'Computer Organization and Design'.

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
build		build
ipcore_dir		ipcore_dir
iseconfig		iseconfig
CPU_TOP.v		CPU_TOP.v
LICENSE		LICENSE
Nexys3_Master.ucf		Nexys3_Master.ucf
README.md		README.md
S_C_C.xise		S_C_C.xise
single_cycle_cpu.bit		single_cycle_cpu.bit
test_alu.v		test_alu.v
test_ctrl.v		test_ctrl.v
test_pc.v		test_pc.v
test_rf.v		test_rf.v
test_rom_a.v		test_rom_a.v
test_se.v		test_se.v
test_t.v		test_t.v

Provide feedback