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[DO NOT MERGE] AIA2.0 - Enable trusty lk log #19
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In the compositor mode of display, dom0/host needs to get the guest framebuffer to do more rendering, so that the guest VM's screen can show up in more fancy way, e.g., in an X window of dom0/host. In order to do that, a new gem object type "gvtbuffer" is introduced to i915. Different from normal gem object in i915, gvtbuffer does not have its own backing storage. Instead, it borrows the page frames of guest VM's framebuffer as its own backing storage. From high level, it works this way: a) gvt notifies kernel/userspace the guest OS page flip by monitoring the related guest MMIO changes and commands. b) user space issue IOCTL to create gvtbuffer gem object. c) kernel creates the gem object, and record the guest FB base address (gfx address) from MMIO. d) When needed, the gvtbuffer will be bound to graphics memory, and be used as normal gem object for rendering. Guest framebuffer must be inside GGTT, whereas the gvtbuffer can be in either GGTT or PPGTT, depending on the requirement of the rendering. Since the gvtbuffer corresponds to the guest framebuffer, which is from guest physical memory, we may not be able to get "page struct" for them. But i915 gem framework has had similar cases. A gem object can have stolen memory as its backing storage. In such case, the backing storage does not have "page struct" as well, and i915 has handled the case in the framework well. This patch was originally from daivid.j.cowperthwaite@intel.com, and pretty some changes were made since then. Change-Id: Ic0821f58dd568217a44b1b478c9659c709889c43 Signed-off-by: Zhiyuan Lv <zhiyuan.lv@intel.com> Reviewed-on: Reviewed-by: He, Min <min.he@intel.com> Reviewed-by: Jiang, Fei <fei.jiang@intel.com> Reviewed-by: Dong, Eddie <eddie.dong@intel.com> Tested-by: Dong, Eddie <eddie.dong@intel.com>
HDMI port enabling will assert port status, if it's already set during reset stage, i915 will pop up warning message. Unset those bits to avoid such warning message. Signed-off-by: Fei Jiang <fei.jiang@intel.com> Change-Id: Ic8c738baa472d7f1086081cb1b634670327aae97
It is to support plane scaling feature, add scaler owner to avoid con-current scaler access. Such ownership is passed from SOS side through pvmmio scaler_owned member. Guest OS patch. Signed-off-by: Fei Jiang <fei.jiang@intel.com>
It is to support plane scaling feature, need let guest access PS_CTRL, PS_WIN, PS_POS registers. Use parameter domain_scaler_owner to control domain's scaler ownership. Validate with IGT test: kms_plane_scaling. SOS only patch. V2: Fix the issue when it writes 0 to PS_CTRL register to disable scaling. Signed-off-by: Min He <min.he@intel.com> Signed-off-by: Fei Jiang <fei.jiang@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
This uint type module parameter is used to control the pvmmio features for MMIO emulation in GVT. This parameter is default 0. Its permission type is 0400 which means user could only change its value through the cmdline, this is to prevent the dynamic modification during runtime which would break the pvmmio internal logic. Notice: this patch is required to be applied to guest kernel. Change-Id: I570f1fe02101e518595c02fce67601b692871aa9 Signed-off-by: Pei Zhang <pei.zhang@intel.com> Signed-off-by: Jiang, Fei <fei.jiang@intel.com> Acknowledged-by: Singh, Satyeshwar <satyeshwar.singh@intel.com> Reviewed-on: Reviewed-by: He, Min <min.he@intel.com> Reviewed-by: Jiang, Fei <fei.jiang@intel.com> Reviewed-by: Dong, Eddie <eddie.dong@intel.com> Tested-by: Dong, Eddie <eddie.dong@intel.com>
To enable pvmmio feature, we need to prepare to regions memory: the mmio memory whose size is 2M for Gen8/9, and the 4K shared page. GVT creates them for every vGPU instance, guest i915 driver will map them to virtual address. Change-Id: Ifcbd0e55783e19125e98036622cd5d08624d34fa Signed-off-by: Pei Zhang <pei.zhang@intel.com> Acknowledged-by: Singh, Satyeshwar <satyeshwar.singh@intel.com> Reviewed-on: Reviewed-by: He, Min <min.he@intel.com> Reviewed-by: Jiang, Fei <fei.jiang@intel.com> Reviewed-by: Dong, Eddie <eddie.dong@intel.com> Tested-by: Dong, Eddie <eddie.dong@intel.com>
If pvmmio is enabled in i915 host driver, guest i915 will read most MMIO register directly, which won't be trapped to host GVT. A small range MMIOs still need trap. They are filtered in a static function. This patch is to implement the pvmmio in guest i915 driver. Also, for the elsp port writting, we will optimize it to leverage pvmmio. Notice: this patch is required in GVTg guest. Change-Id: I8d51430015822976450c14085979460b9cc021d7 Signed-off-by: Pei Zhang <pei.zhang@intel.com> Acknowledged-by: Singh, Satyeshwar <satyeshwar.singh@intel.com> Reviewed-on: Reviewed-by: He, Min <min.he@intel.com> Reviewed-by: Jiang, Fei <fei.jiang@intel.com> Reviewed-by: Dong, Eddie <eddie.dong@intel.com> Tested-by: Dong, Eddie <eddie.dong@intel.com>
If pvmmio is enabled in i915 host driver, guest i915 will read most MMIO register directly, which won't be trapped to host GVT. A small range MMIOs still need trap. They are filtered in a static function, and this patch is to implement the handler of these registers in GVTg. Also, when pvmmio is enabled, we will optimize ELSP port writing, to reduce the mmio trap numbers from 4 to 1, which can improve the guest GPU performance. Change-Id: Ic72a87499baabe9b3b2fbb5ad827e6ae062ff959 Signed-off-by: Pei Zhang <pei.zhang@intel.com> Acknowledged-by: Singh, Satyeshwar <satyeshwar.singh@intel.com> Reviewed-on: Reviewed-by: He, Min <min.he@intel.com> Reviewed-by: Jiang, Fei <fei.jiang@intel.com> Reviewed-by: Dong, Eddie <eddie.dong@intel.com> Tested-by: Dong, Eddie <eddie.dong@intel.com>
This patch added the pvmmio support in preemption context submission for gvt-g guest. And because GVT-g doesn't support preemption in guests, this patch also disabled preempttion in guest. Signed-off-by: Fei Jiang <fei.jiang@intel.com>
On VGPU scenario the read/write operation of fence_reg will be trapped by the GVT-g. Then gvt-g follows the HW spec to program the fence_reg. And the gvt-g takes care of updating the fence reg correctly for any trapped value of fence reg. So it is unnecessary to read/write fence reg several times. It is enough that the fence reg is written only value in 64-bit mode. This will help to reduce the redundant trap of fence_reg mmio operation. V1->V2: Add back the condition judgement of !pipelined Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: He Min <min.he@intel.com>
…ogether Previously we only support single pci_command writing trap. While when system suspends, pci_command and pci_status are written together in 32 bits, GVT-g also need trap them in such scenario. Signed-off-by: Fei Jiang <fei.jiang@intel.com>
It is performance optimization to reduce plane related register trap counter. When update plane, multiple plane related registers are updated together, optimize it to firstly cache all register values in share page, then only PLANE_SURF register writing is trapped. Plane pvmmio level is PVMMIO_PLANE_UPDATE. Patch for both SOS and UOS. V2: add memset tmp_plane to be more safer and add more commit description Signed-off-by: Fei Jiang <fei.jiang@intel.com> Reviewed-by: Min He <min.he@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
When pvmmio level PVMMIO_PLANE_UPDATE is enabled, need handle multiple plane related registers updating together when PLANE_SURF is traped. sos only patch. V2: restore sequence of skl_plane_mmio_write/skl_plane_mmio_write and skl_plane_surf_write, while need add extra declarations. Signed-off-by: Fei Jiang <fei.jiang@intel.com> Reviewed-by: Min He <min.he@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
plane update pvmmio level is 0x2, need set it in enable_pvmmio for both SOS and UOS kernel driver. Patch for both SOS and UOS. Signed-off-by: Fei Jiang <fei.jiang@intel.com> Reviewed-by: Min He <min.he@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
If hypervisor is implementing identical 1:1 memory mapping for sos kernel, sos gpa equals to hpa, so we don't need call hypercall for gfn_to_mfn. Currently this is a hack solution in function is_identical_mmap, later hypervisor will provide one hypercall to let SOS query such kind of info. V2: add error handling, if map_guest_phys fail, still call vhm_gpa2hpa Signed-off-by: Fei Jiang <fei.jiang@intel.com>
During shadow ppgtt update, we need call intel_gvt_hypervisor_read_gpa every entry for whole ppgtt page, for performance consideration, optmize it by firstly reading whole page ppgtt gpa content into one scratch page, then following read_gpa directly read from scratch page. Have vgpu->ge_cache_enable to control, currently we only cache in ppgtt_populate_shadow_page for pte update case. Signed-off-by: Fei Jiang <fei.jiang@intel.com> Reviewed-by: Min He <min.he@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
MI_NOOP is a common command appearing in almost all command buffers, put it into a fastpath can improve perfomance, especially in command buffers contains lots of MI_NOOPs (0s). Take glmark2 as an example, 3% performance increase is observed after introduced this patch. Meanwhile, in case where abundant in MI_NOOPs, up to 12% performance increase is measured. v2: use lowercase for index of MI_NOOP in cmd_info (zhenyu wang) Signed-off-by: Li Weinan <weinan.z.li@intel.com> Signed-off-by: Zhao Yan <yan.y.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: He, Min <min.he@intel.com>
This patch extends g2v notification to notify host GVT-g of ppgtt update from guest, including alloc_4lvl, clear_4lv4 and insert_4lvl. It uses shared page to pass the additional params. This patch also add one new pvmmio level to control ppgtt update. This patch is needed for both uos and sos v2: - create a struct for ppggt update in shared page. - use multiple notifications in case insert size is too big. v3: - not pass pd pages, let GVT-g read from guest memory instead. v4: - not change rsvd2 type. v5: - pass cache_level to GVT-g Tracked-On: #874 Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com> Reviewed-by: He, Min <min.he@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
This patch handles ppgtt update from g2v notification. It read out ppgtt pte entries from guest pte tables page and convert them to host pfns. It creates local ppgtt tables and insert the content pages into the local ppgtt tables directly, which does not track the usage of guest page table and removes the cost of write protection from the original shadow page mechansim. This patch is only for sos. v3: - Not pass pd pages, let GVT-g read from guest memory instead. v4: - fix page walk error. - remove insert_4lvl_sg. v5: - use cache_level from guest. Tracked-On: #874 Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com> Reviewed-by: He, Min <min.he@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
This patch enables pv ppgtt update by default. It is needed for both uos and sos. Tracked-On: #874 Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com> Reviewed-by: He, Min <min.he@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
It is performance optimization to reduce plane wm related register trap counter. When update plane wm, multiple plane wm related registers are updated together, optimize it to firstly cache all register values in share page, then only PLANE_NV12_BUF_CFG register writing is trapped. Plane pvmmio level is PVMMIO_PLANE_WM_UPDATE. If plane restriction feature is enabled, trap handlers for plane wm related register are null, then directly return. Patch for both SOS and UOS. V2: when plane restriction feature is enabled, SOS trap handlers for plane wm related registers are null, then don't trap Signed-off-by: Fei Jiang <fei.jiang@intel.com> Reviewed-by: Min He <min.he@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
When pvmmio level PVMMIO_PLANE_WM_UPDATE is enabled, need handle multiple plane wm related registers updating when PLANE_NV12_BUF_CFG writing is traped. sos only patch. Signed-off-by: Fei Jiang <fei.jiang@intel.com> Reviewed-by: Min He <min.he@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
plane wm update pvmmio level is 0x4, need set it in enable_pvmmio for both SOS and UOS kernel driver. Patch for both SOS and UOS. V2: use PVMMIO_PLANE_WM_UPDATE bit definition to improve readability Signed-off-by: Fei Jiang <fei.jiang@intel.com> Reviewed-by: Min He <min.he@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com>
This patch extends g2v notification to notify host GVT-g of ggtt update from guest, including ggtt_insert_entries and ggtt_clear_range. This patch also add one new pvmmio level to control ggtt update. This patch is needed for both uos and sos. v2: - calculate num_entries from gtt_entries. v3: - pass cache_level to GVT-g - consolidate the same code into a function. Tracked-On: projectacrn/acrn-hypervisor#994 Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com> Reviewed-by: He, Min <min.he@intel.com>
This patch handles ggtt update from g2v notification. It maps the physical pages behind virtual page table to guest, so guest can update its pte entries directly to avoid mmio trap. Then guest ggtt pte entries are converted to host pte entries and inserted into host gtt table. The tricky part is that pvmmio parameter detection is later than virtual page trable creation and pci bar address update, So the map ggtt mmio is done during pvmmio param detection. This patch is only for sos. v2: - cut invalid range. - release gfn to mfn mapping when free gtt. v3: - call ggtt insert_entries function - add size check in validate_ggtt_range - rename trap to map V4: Fall back to disable ggtt PV when it fails to alloc 2M pages for GGTT pV. Tracked-On: projectacrn/acrn-hypervisor#994 Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com> Reviewed-by: He, Min <min.he@intel.com>
This patch enables pv ggtt update by default. It is needed for both uos and sos. Tracked-On: projectacrn/acrn-hypervisor#994 Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com> Reviewed-by: He, Min <min.he@intel.com>
…calling for hypervisor Now hypervisor adds strict checks when the sos tries to add/delete the mapping between gfn and mfn. In such case it should check the state of PVMMIO gtt table to avoid the incorrect hyper call. If the mapping between gfn and mfn is not setup for PVMMIO GTT, it should not remove the mapping. Otherwise the hypervisor will report that the mapping doesn't exist. Tracked-On: projectacrn/acrn-hypervisor#1158 Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: He, Min <min.he@intel.com>
This patch add back the ddb allocation for the PLANE_CURSOR and allocate ddb according to current active pipes. In this way, this patch can support 4K monitors and fix the issue that cursor not work when enable_initial_modeset is 0. v2: - correct ddb start calculation Tracked-On: projectacrn/acrn-hypervisor#1171 Signed-off-by: Zhipeng Gong <zhipeng.gong@intel.com> Reviewed-by: Zhao Yakui <yakui.zhao@intel.com> Reviewed-by: Fei Jiang <fei.jiang@intel.com>
This commit squishes all the different commits related to the hyper_dmabuf driver into one. This driver is currently under reiview upstream: https://lists.freedesktop.org/archives/dri-devel/2018-February/165720.html Once the review is done upstream, the relevant changes between this version and the upstream one need to be synced. Upload of intial version of hyper_DMABUF driver enabling DMA_BUF exchange between two different VMs in virtualized platform based on hypervisor such as KVM or XEN. Hyper_DMABUF drv's primary role is to import a DMA_BUF from originator then re-export it to another Linux VM so that it can be mapped and accessed by it. The functionality of this driver highly depends on Hypervisor's native page sharing mechanism and inter-VM communication support. This driver has two layers, one is main hyper_DMABUF framework for scatter-gather list management that handles actual import and export of DMA_BUF. Lower layer is about actual memory sharing and communication between two VMs, which is hypervisor-specific interface. This driver is initially designed to enable DMA_BUF sharing across VMs in Xen environment, so currently working with Xen only. This also adds Kernel configuration for hyper_DMABUF drv under Device Drivers->Xen driver support->hyper_dmabuf options. To give some brief information about each source file, hyper_dmabuf/hyper_dmabuf_conf.h : configuration info hyper_dmabuf/hyper_dmabuf_drv.c : driver interface and initialization hyper_dmabuf/hyper_dmabuf_imp.c : scatter-gather list generation and management. DMA_BUF ops for DMA_BUF reconstructed from hyper_DMABUF hyper_dmabuf/hyper_dmabuf_ioctl.c : IOCTLs calls for export/import and comm channel creation unexport. hyper_dmabuf/hyper_dmabuf_list.c : Database (linked-list) for exported and imported hyper_DMABUF hyper_dmabuf/hyper_dmabuf_msg.c : creation and management of messages between exporter and importer hyper_dmabuf/xen/hyper_dmabuf_xen_comm.c : comm ch management and ISRs for incoming messages. hyper_dmabuf/xen/hyper_dmabuf_xen_comm_list.c : Database (linked-list) for keeping information about existing comm channels among VMs Signed-off-by: Kim, Dongwon <dongwon.kim@intel.com> Signed-off-by: Matuesz, Polrola <mateuszx.potrola@intel.com>
The hyper_dmabuf driver is designed and tested only on x86/x86_64 architecture based systems. Therefore, disable it when trying to build for other architectures. Signed-off-by: Vivek Kasireddy <vivek.kasireddy@intel.com> Reviewed-by: Mateusz Polrola <mateuszx.potrola@intel.com>
DAL user space interface allows sending and receiving of DAL messages, from and to user-space, usually between JHI server to DAL FW. DAL module is in pass-through mode. This patch adds the character device interface. Change-Id: I5f6d2c17744ad2481387c9a4427c8de5962bca8d Signed-off-by: Yael Samet <yael.samet@intel.com>
DAL kernel space interface exposes in-kernel API to access trusted execution service in DAL. The API is defined in <linux/dal.h> header file. Change-Id: Ief3de92c3674ce8a21375bc11da38f1ae5fc3cc6 Signed-off-by: Yael Samet <yael.samet@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
The exclusive access option allows a kernel space client to restrict access to specified trusted application. When some applet was marked as exclusive by a kernel space client, no user space client will be allowd to create a session with this applet. Change-Id: Ib9397bf9c5a0cd911cf9ca577302c99384782629 Signed-off-by: Yael Samet <yael.samet@intel.com>
Documentation under Documentation/misc-devices/mei/dal Change-Id: If6dd132e3c80397ec8f2dc324ee215d8372cfb41 Signed-off-by: Yael Samet <yael.samet@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com>
DAL test module allows the user space to test the DAL kernel space api. It exposes a character device to the user space, and calls DAL api's according to the protocol which is defined in kdi_cmd_defs.h header file. This patch adds the code of DAL test module. Change-Id: Id7ec2e7d3f22b07c41941dc5bada6edaf16e893b Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Yael Samet <yael.samet@intel.com>
The keystore driver is designed to provide a secure storage solution for secret keys in TEE environment. The basic functions it provides including: register/unregister, generate key, wrap key, load key/unload key, and encrypt/decrypt, etc. Applications interface is through the char device ioctls on /dev/keystore. Change-Id: Id181c9d469b7ff865efbe368a2c35a1803ff9634 Signed-off-by: Cliff Cai <cliff.cai@intel.com>
This patch fixed a memory leak issue in GVT-g, which leads to memory corruption during guest create/destroy cycles. Also removed some unnecessary warnings in this patch. Signed-off-by: Min He <min.he@intel.com>
Change-Id: I96baf5e7172ee281884e01c40f03e79fa68384ba
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Change-Id: I9cdff6da767cc7ede7d42213d08fed9b43564b90 Signed-off-by: Gross, Mark <mark.gross@intel.com>
Change-Id: I6d917ac606e6a53c4f79491bbd7923580c0eb99d
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Change-Id: Ia7e22f6774181c3ad2fdc136ef4bc56ec9c9cc52 Signed-off-by: Gross, Mark <mark.gross@intel.com>
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Change-Id: Ieed38985b3f0297bce8c2594a8600f4f0c9daf61 Signed-off-by: Gross, Mark <mark.gross@intel.com>
Change-Id: I12ced4273e3106c4bb069ebbdb8f3db49d2901d6
Change-Id: I2f8363976483b235cae0ac6ec19611bd1537f60a Signed-off-by: Gross, Mark <mark.gross@intel.com>
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Change-Id: I0248da054ac08235d7a3be87e8608ff0bc81e7c0
…19/mainline-tracking-v419.h * commit '19ba0ce55a5b0361abb6a3fa45ea6281e8c80828': (724 commits) drm/i915/gvt: fixed a memory leak issue in gtt.c security: add keystore driver support mei: dal: add test module mei: dal: add module Documentation mei: dal: add exclusive access menagement mei: dal: add kernel space interface mei: dal: add character device for user space interface mei: dal: dynamic application loader mei: dal: add bh plugin code mei: dal: add acp parser code mei: virtio: [V13] virtualization frontend driver mei: bus: unconditionally enable clients with vm support mei: bus: add more client attributes to sysfs mei: expose device state in sysfs mei: bus: use zero vtag for bus clients. mei: free read cb on ctrl_wr list flush mei: flush only objects belonging to fp in non-final flush mei: keep pending read on one client disconnect mei: add connect with vtag ioctl mei: add a spin lock to protect rd_completed queue ...
…19/mainline-tracking-android-v419.h * commit '01c14a73ff0d65a6bec9934e6ecd2c21cc6c987f': (551 commits) alarmtimer: add config to skip suspend flow move sdhci-pci & mmc_block to fs_initcall_sync disbale SD/SDIO on EMMC bus Turbo CPU freq before kernel decompress ANDROID: sdcardfs: fix -ENOENT lookup race issue on AOSP sdcardfs pstore: add license for intel pstore pram driver staging: android: fwdata: add missing MODULE_LICENSE watchdog: add an IRQ handler to dump log on first timeout When kernel crash, save the reboot reason to EFI variable. Increase COMMAND_LINE_SIZE from 2048 to 4096 wdt:reboot at second watchdog timeout Debug: Warning: Only fix some build warnings Flush CPU cache before reboot on panic Sbl: Klocwork: Fix the potential issue of sbl code kernel: ipc1: add a read-only attribute for PMC ssram base Kernel: Fix below potential issue in dvctrace c file ablbc: revert patches of panic and revise logic Fix compile warning in watchdog abl and sbl are only used for x86 intel_th: sync "intel_th_alloc" function for ACPI ...
Print trusty lk log to dmesg. Change-Id: Ic7af1ad7f60dd1864b3185e0a61c64a8bfac701b Signed-off-by: swei22 <w.sheng@intel.com>
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Print trusty lk log to dmesg.
Change-Id: Ic7af1ad7f60dd1864b3185e0a61c64a8bfac701b
Signed-off-by: swei22 w.sheng@intel.com