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added 7 commits
January 24, 2015 21:54
…te change to log file.
Timer decreased when instruction tracing enabled, to compensate for slowdown.
with interrupts disabled.
It was not quite random and did not skip Wired entries.
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(3) Is not correct. There was a specific change in the specification to cover this situation. See CP0 Config7, WII bit. |
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Well, none of MIPS cores currently supported by QEMU has Config7.WII bit set, so my change does not break anything. Though I agree that it makes sense to add a condition "! (env->CP0_Config7 & (1 << CP0C7_WII))" to avoid termination of simulate in case WII bit is enabled. |
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This pull request consists of eight commits to be applied in series.
(1) This change adds a new feature: option "-d instr". It enables printing of all executed MIPS instructions to log file. It also prints the modified cpu registers, TLB entries and memory load/store transactions. The information is printed in the following format:
(2) Make the CPU clock frequency configurable per platform. Currently the clock rate for all MIPS platforms is fixed at 100MHz. Need to make it 40MHz for pic32mx7.
(3) When WAIT instruction is executed with interrupts disabled, the processor is essentially suspended forever. Terminate the simulation in this case.
(4) For TLBWR instruction, the generated random index value has been not quite random and did not take into account the Wired register value. Fixed.
(5) Added support for external interrupt controller mode (EIC). Required for pic32.
(6) Added two processor variants: M4K and microAptivUP. Needed for pic32mx and pic32mz simulation.
(7) Added two machine platforms: Microchip pic32mx7 and pic32mz microcontrollers. Several board types supported for each platform:
(8) Ethernet device implemented for pic32mz.
For examples of real pic32 applications running on QEMU, see page: https://github.com/sergev/qemu/wiki