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Added
boxcar: Add boxcar function to compose bit masksheaviside: Add Heaviside function to compose bit masksring_buffer: Add ring buffer with sequential write and random readstrip_counter: Add counter with 'trip' output when reaching threshold valueChanged
cb_filter,id_queue,lzc,rr_arb_tree: Speed up Verilator simulationcdc_fifo_gray*,isochronous_spill_register: Change flip-flops without to flip-flops with resetisochronous_spill_register: Remove unnecessary data stability assertionsaddr_decode*: Change assumed integer index to arbitrary type (default remains integer)Fixed
id_queue: Fix struct accesscdc_fifo_gray*: Fix Spyglass linting edge caselzc: Fix assertion for degenerate caseWIDTH == 0