Draft: Prasadar/multi precision

[FrancescoConti]

This pull request introduces significant updates to the HCI (Hardware Communication Interface) modules, focusing on improving support for flexible element and bank widths, enhancing address generation, and updating related data alignment logic. The changes modernize the streaming and routing modules to support parameterized data widths and more generic, scalable memory banking, and update address generation logic to version 4. Below are the most important changes grouped by theme:

1. Parameterization and Data Alignment Enhancements

• Added new parameters (ELEMENT_WIDTH, ELEMENTS_PER_BANK, etc.) to both hci_core_sink and hci_core_source modules, enabling more flexible configuration of element and bank widths. This includes calculation of derived localparams for data alignment and addressing. (rtl/core/hci_core_sink.sv [1] [2]; rtl/core/hci_core_source.sv [3] [4] [5]
• Updated data alignment logic in both sink and source modules to utilize the new parameters, supporting more generic and scalable data realignment for misaligned accesses. (rtl/core/hci_core_sink.sv [1]; rtl/core/hci_core_source.sv [2] [3]

2. Address Generation and Interface Updates

• Migrated address generation from addressgen_v3 to addressgen_v4 in both sink and source modules, and updated associated control and flag structures in the common package. (rtl/common/hci_package.sv [1]; rtl/core/hci_core_sink.sv [2]; rtl/core/hci_core_source.sv [3]
• Updated address calculation and handling to support variable element/bank widths, including changes to how addresses are constructed and aligned for memory accesses. (rtl/core/hci_core_sink.sv [1]; rtl/core/hci_core_source.sv [2]

3. Router Module Generalization

• Generalized the hci_router module to support configurable bank word and element widths, updating all relevant localparams and logic for data, byte enable, and address calculation. (rtl/interco/hci_router.sv [1] [2] [3] [4] [5]
• Improved address calculation for bank-level addressing and data routing, using new parameters for flexible memory organization. (rtl/interco/hci_router.sv rtl/interco/hci_router.svL193-R209)

4. Miscellaneous and Protocol Updates

• Added no_valid_transfers flag to the streamer flags structure and its assignment in the sink, to signal when no transfers are in flight. (rtl/common/hci_package.sv [1]; rtl/core/hci_core_sink.sv [2]
• Updated assertion logic and various protocol assignments to align with new parameterization and improved interface consistency. (rtl/core/hci_core_sink.sv [1]; rtl/core/hci_core_source.sv [2]

These updates collectively make the HCI modules more flexible, scalable, and maintainable, supporting a wider range of memory configurations and improving the robustness of data streaming and routing.