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0322033
Add relOBI encoding and decoding modules
micprog May 18, 2024
e484658
Add relobi demux
micprog Aug 14, 2024
884ccd5
Update redundancy_cells
micprog Sep 30, 2024
8a03311
Add explanatory comments to OBI IPs.
micprog Sep 30, 2024
19ab1de
Extract a_other enc/dec
micprog Sep 30, 2024
5a2e9ed
WIP: Add relobi mux
micprog May 6, 2025
c0719ad
Add r_other_enc/dec
micprog May 8, 2025
2522c24
Update relobi mux
micprog May 8, 2025
b84b620
Add relobi xbar
micprog May 8, 2025
3de4596
Fix relobi, add xbar test
micprog May 8, 2025
9126de7
Add fault signalling
micprog May 9, 2025
6c4a4c3
Enable VCS flow
micprog May 20, 2025
4658ff0
Add VCS flow to CI
micprog May 26, 2025
47939f5
Cleanup obi xbar interface variant
micprog May 26, 2025
522019d
Fix optional types for vsim
micprog May 26, 2025
9c30d2b
Bump questa version to avoid workaround
micprog Jun 10, 2025
3e514d1
Fix vcs/lint issues
micprog Jun 10, 2025
1ded75a
Gate hsiao faults
micprog Jun 10, 2025
6c8cfbe
Properly handle rid resizing in mux
micprog Jun 10, 2025
dc5cc51
Add fault tracking to TB
micprog Jun 10, 2025
ca71161
Update fault tracking
micprog Jun 13, 2025
9796464
Update tb_relobi_xbar for concurrent FI
micprog Jun 16, 2025
5f2ff6f
Fix relobi_demux cnt signals for correct error behavior
micprog Jun 17, 2025
5680d72
Fix lint
micprog Jun 18, 2025
38d79ee
Bump redundancy_cells to commit on main
micprog Jun 18, 2025
6714ef4
Fix lint
micprog Jun 18, 2025
4ba7763
relobi: add cuts to xbar tb
micprog Jul 4, 2025
1f80d6a
Add relobi cut
micprog Jul 4, 2025
7acd1c6
Add vcs flags for lint
micprog Jul 4, 2025
073d458
Simplify obi cut
micprog Jul 4, 2025
e0b68e2
alter obi test parameters for more appropriate xbar behavior
micprog Jul 4, 2025
cc63c83
Partition out relobi tmr parts
micprog Jul 4, 2025
8c79496
Add corrector IPs
micprog Jul 14, 2025
e66a71a
Update relobi IPs
micprog Jul 14, 2025
4cace52
Fixes/updates from testing
micprog Jul 29, 2025
dfcfedf
Bump redundancy cells for ecc width fix
micprog Jul 30, 2025
4601fa1
Correct relobi_err_sbr
micprog Jul 30, 2025
949657a
Add relobi sram shim with rmw
micprog Jul 30, 2025
7973246
Add obi_to_apb module
micprog Aug 4, 2025
b0664ff
Fix relobi_err_sbr
micprog Aug 5, 2025
558594f
Bump redundancy_cells
micprog Aug 11, 2025
ea32b16
Fix CI
micprog Aug 11, 2025
f2dc6d6
update for relOBI testing
micprog Sep 9, 2025
efb34a7
Add scrubber to relobi sram shim
micprog Oct 17, 2025
588b4da
Add obi isolate
micprog Nov 7, 2025
2b279c8
Add relobi isolate
micprog Nov 7, 2025
bf55dc0
Fix obi isolate parameter name
micprog Nov 10, 2025
b9b94d1
Fixes
micprog Nov 12, 2025
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3 changes: 3 additions & 0 deletions .gitignore
Original file line number Diff line number Diff line change
@@ -1 +1,4 @@
.bender
working_dir
build
fault_sim
17 changes: 8 additions & 9 deletions .gitlab-ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -3,20 +3,19 @@
# SPDX-License-Identifier: SHL-0.51

stages:
- build
- sim

variables:
VSIM: "questa-2022.3 vsim"
VSIM: "questa-2025.1-dz vsim"
VCS: "vcs-2024.09-zr vcs"
VLOGAN: "vcs-2024.09-zr vlogan"

build:
stage: build
sim:
stage: sim
script:
- make build
- make all_vsim

sim:
sim-vcs:
stage: sim
dependencies:
- build
script:
- make all
- make all_vcs
40 changes: 38 additions & 2 deletions Bender.lock
Original file line number Diff line number Diff line change
@@ -1,4 +1,20 @@
packages:
apb:
revision: 77ddf073f194d44b9119949d2421be59789e69ae
version: 0.2.4
source:
Git: https://github.com/pulp-platform/apb.git
dependencies:
- common_cells
axi:
revision: f07498d53ecd5518b277c7d213ec3b71ca4df93c
version: 0.39.7
source:
Git: https://github.com/pulp-platform/axi.git
dependencies:
- common_cells
- common_verification
- tech_cells_generic
common_cells:
revision: 9afda9abb565971649c2aa0985639c096f351171
version: 1.38.0
Expand All @@ -8,11 +24,31 @@ packages:
- common_verification
- tech_cells_generic
common_verification:
revision: 9c07fa860593b2caabd9b5681740c25fac04b878
version: 0.2.3
revision: fb1885f48ea46164a10568aeff51884389f67ae3
version: 0.2.5
source:
Git: https://github.com/pulp-platform/common_verification.git
dependencies: []
redundancy_cells:
revision: 766e376b7ddb70e744740e703a371f7fe7cc3e74
version: null
source:
Git: https://github.com/pulp-platform/redundancy_cells.git
dependencies:
- common_cells
- common_verification
- register_interface
- tech_cells_generic
register_interface:
revision: 5daa85d164cf6b54ad061ea1e4c6f3624556e467
version: 0.4.5
source:
Git: https://github.com/pulp-platform/register_interface.git
dependencies:
- apb
- axi
- common_cells
- common_verification
tech_cells_generic:
revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
version: 0.2.13
Expand Down
41 changes: 40 additions & 1 deletion Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@ package:
dependencies:
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.38.0 }
common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 }
redundancy_cells: { git: "https://github.com/pulp-platform/redundancy_cells.git", rev: 766e376b7ddb70e744740e703a371f7fe7cc3e74 }

export_include_dirs:
- include
Expand All @@ -21,6 +22,7 @@ sources:
- src/obi_intf.sv
- src/obi_rready_converter.sv
- src/apb_to_obi.sv
- src/obi_to_apb.sv
# Level 3
- src/obi_atop_resolver.sv
- src/obi_cut.sv
Expand All @@ -29,12 +31,49 @@ sources:
- src/obi_mux.sv
- src/obi_sram_shim.sv
# Level 4
- src/obi_isolate.sv
- src/obi_xbar.sv
- target: test
- target: any(test, obi_test)
files:
- src/test/obi_asserter.sv
- src/test/obi_test.sv
- src/test/obi_sim_mem.sv
- src/test/tb_obi_xbar.sv
- src/test/atop_golden_mem_pkg.sv
- src/test/tb_obi_atop_resolver.sv

- target: relOBI
files:
# Level 1
- src/relobi_pkg.sv
- src/relobi_tmr_r.sv
# Level 2
- src/relobi_a_other_decoder.sv
- src/relobi_a_other_encoder.sv
- src/relobi_a_other_corrector.sv
- src/relobi_r_other_decoder.sv
- src/relobi_r_other_encoder.sv
- src/relobi_r_other_corrector.sv
# Level 3
- src/relobi_decoder.sv
- src/relobi_encoder.sv
- src/relobi_corrector.sv
# Level 4
- src/relobi_cut.sv
- src/relobi_demux.sv
- src/relobi_err_sbr.sv
- src/relobi_mux.sv
- src/relobi_sram_shim.sv
# Level 5
- src/relobi_isolate.sv
- src/relobi_xbar.sv
- target: any(test, obi_test)
files:
- target: ZOIX
files:
- src/test/tb_relobi_xbar.sv
include_dirs:
- fault_sim
- target: not(ZOIX)
files:
- src/test/tb_relobi_xbar.sv
71 changes: 58 additions & 13 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -4,32 +4,77 @@

BENDER ?= bender
VSIM ?= vsim
VCS ?= vcs
VLOGAN ?= vlogan

AVAILABLE_TESTBENCHES = tb_obi_xbar tb_obi_atop_resolver
BENDER_TARGETS := -t obi_test
BENDER_TARGETS += -t relOBI

scripts/compile.tcl:
AVAILABLE_TESTBENCHES = tb_obi_xbar tb_obi_atop_resolver tb_relobi_xbar

TBS_VSIM = $(addsuffix _vsim, $(AVAILABLE_TESTBENCHES))
TBS_VCS = $(addsuffix _vcs, $(AVAILABLE_TESTBENCHES))

# QuestaSim Flow
scripts/compile_vsim.tcl: Bender.yml Bender.lock
mkdir -p scripts
$(BENDER) script vsim -t test --vlog-arg="-svinputport=compat" > $@
$(BENDER) script vsim $(BENDER_TARGETS) --vlog-arg="-svinputport=compat" > $@

.PHONY: build
build: scripts/compile.tcl
$(VSIM) -c -do 'exit -code [source scripts/compile.tcl]'
.PHONY: build_vsim
build_vsim: scripts/compile_vsim.tcl
$(VSIM) -c -do 'exit -code [source scripts/compile_vsim.tcl]'

.PHONY: $(AVAILABLE_TESTBENCHES)
$(AVAILABLE_TESTBENCHES): build
.PHONY: $(TBS_VSIM)
$(TBS_VSIM): build_vsim
ifdef gui
$(VSIM) $@ -voptargs="+acc"
$(VSIM) $(patsubst %_vsim, %, $@) -voptargs="+acc"
else
$(VSIM) -c $@ -do "run -all; quit -f"
$(VSIM) -c $(patsubst %_vsim, %, $@) -voptargs="+acc" -do "run -all; quit -f"
endif

.PHONY: all
all: $(AVAILABLE_TESTBENCHES)
.PHONY: all_vsim
all_vsim: $(TBS_VSIM)

# VCS Flow
VCS_SCRIPT_ARGS += -assert svaext +v2k -override_timescale=10ns/10ps -kdb
VCS_COMPILE_ARGS += -debug_access+all -override_timescale=10ns/10ps
VCS_COMPILE_ARGS += +lint=TFIPC-L +lint=PCWM +warn=noCWUC +warn=noUII-L
VCS_RUNTIME_ARGS =

scripts/compile_vcs.sh: Bender.yml Bender.lock
mkdir -p scripts
$(BENDER) script vcs --vlogan-bin="$(VLOGAN)" $(BENDER_TARGETS) --vlog-arg="$(VCS_SCRIPT_ARGS)" > $@

.PHONY: build_vcs
build_vcs: scripts/compile_vcs.sh
mkdir -p build
chmod +x scripts/compile_vcs.sh
cd build && ../scripts/compile_vcs.sh

build/%.sim: build_vcs
@if ! echo "$(AVAILABLE_TESTBENCHES)" | grep -wq "$*"; then \
echo "Error: $(basename $@) is not an available testbench"; \
echo "Available testbenches: $(AVAILABLE_TESTBENCHES)"; \
exit 1; \
fi
cd build && \
$(VCS) $(VCS_COMPILE_ARGS) -o $*.sim $*

.PHONY: $(TBS_VCS)
$(TBS_VCS):
@echo "Running VCS simulation for $@ as $(patsubst %_vcs,%,$@)"
$(MAKE) build/$(patsubst %_vcs,%,$@).sim
build/$(patsubst %_vcs,%,$@).sim $(VCS_RUNTIME_ARGS)

.PHONY: all_vcs
all_vcs: $(TBS_VCS)

.PHONY: clean
clean:
rm -f scripts/compile.tcl
rm -f scripts/compile_vsim.tcl
rm -rf work
rm -f modelsim.ini
rm -f transcript
rm -f vsim.wlf
rm -f scripts/compile_vcs.sh
rm -rf build
69 changes: 4 additions & 65 deletions include/obi/assign.svh
Original file line number Diff line number Diff line change
Expand Up @@ -27,46 +27,11 @@
__opt_as __lhs``__lhs_sep``r_optional = __rhs``__rhs_sep``r_optional;
`define __OBI_TO_REQ(__opt_as, __lhs, __lhs_sep, __rhs, __rhs_sep, __lhscfg, __rhscfg) \
`__OBI_TO_A(__opt_as, __lhs, __lhs_sep, __rhs, __rhs_sep) \
__opt_as __lhs.req = __rhs.req; \
if (__lhscfg.UseRReady) begin \
if (__rhscfg.UseRReady) begin \
__opt_as __lhs.rready = __rhs.rready; \
if (__lhscfg.Integrity) begin \
if (__rhscfg.Integrity) begin \
__opt_as __lhs.rreadypar = __rhs.rreadypar; \
end else begin \
__opt_as __lhs.rreadypar = ~__rhs.rready; \
end \
end \
end else begin \
__opt_as __lhs.rready = 1'b1; \
if (__lhscfg.Integrity) begin \
__opt_as __lhs.rreadypar = 1'b0; \
end \
end \
end else if (__rhscfg.UseRReady) begin \
$error("Incompatible Configs! Please assign manually!"); \
end \
if (__lhscfg.Integrity) begin \
if (__rhscfg.Integrity) begin \
__opt_as __lhs.reqpar = __rhs.reqpar; \
end else begin \
__opt_as __lhs.reqpar = ~__rhs.req; \
end \
end
__opt_as __lhs.req = __rhs.req;
`define __OBI_TO_RSP(__opt_as, __lhs, __lhs_sep, __rhs, __rhs_sep, __lhscfg, __rhscfg) \
`__OBI_TO_R(__opt_as, __lhs, __lhs_sep, __rhs, __rhs_sep) \
__opt_as __lhs.gnt = __rhs.gnt; \
__opt_as __lhs.rvalid = __rhs.rvalid; \
if (__lhscfg.Integrity) begin \
if (__rhscfg.Integrity) begin \
__opt_as __lhs.gntpar = __rhs.gntpar; \
__opt_as __lhs.rvalidpar = __rhs.rvalidpar; \
end else begin \
__opt_as __lhs.gntpar = ~__rhs.gnt; \
__opt_as __lhs.rvalidpar = ~__rhs.rvalid; \
end \
end
__opt_as __lhs.rvalid = __rhs.rvalid;
////////////////////////////////////////////////////////////////////////////////////////////////////


Expand All @@ -86,36 +51,10 @@
`define OBI_ASSIGN_A(dst, src, dstcfg, srccfg) \
`__OBI_TO_A(assign, dst, ., src, .) \
assign dst.req = src.req; \
assign src.gnt = dst.gnt; \
if (dstcfg.Integrity && srccfg.Integrity) begin \
assign dst.reqpar = src.reqpar; \
assign src.gntpar = dst.gntpar; \
end else if (dstcfg.Integrity ^ srccfg.Integrity) begin \
$error("Incompatible Configs! Please assign manually!"); \
end
assign src.gnt = dst.gnt;
`define OBI_ASSIGN_R(dst, src, dstcfg, srccfg) \
`__OBI_TO_R(assign, dst, ., src, .) \
assign dst.rvalid = src.rvalid; \
if (dstcfg.Integrity && srccfg.Integrity) begin \
assign dst.rvalidpar = src.rvalidpar; \
end else if (dstcfg.Integrity ^ srccfg.Integrity) begin \
$error("Incompatible Configs! Please assign manually!"); \
end \
if (srccfg.UseRReady) begin \
if (dstcfg.UseRReady) begin \
assign src.rready = dst.rready; \
if (srccfg.Integrity && dstcfg.Integrity) begin \
assign src.rreadypar = dst.rreadypar; \
end \
end else begin \
assign src.rready = 1'b1; \
if (srccfg.Integrity) begin \
assign src.rreadypar = 1'b0; \
end \
end \
end else if (dstcfg.UseRReady) begin \
$error("Incompatible Configs! Please assign manually!"); \
end
assign dst.rvalid = src.rvalid;
`define OBI_ASSIGN(sbr, mgr, sbrcfg, mgrcfg) \
`OBI_ASSIGN_A(sbr, mgr, sbrcfg, mgrcfg) \
`OBI_ASSIGN_R(mgr, sbr, mgrcfg, sbrcfg)
Expand Down
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