Allow assertions exclusion with a define.

[yvantor]

This PR introduces the OBI_ASSERT_ON define to shut down System Verilog assertions in the apb_2_obi IP. This became useful when simulating code with Verilator since it complains about:

%Error: [...]/apb_to_obi.sv:142:132: Define passed too many arguments: ASSERT
  142 |   ASSERT(penable, obi_phase_q == RESP |-> apb_req_i.penable, clk_i, !rst_ni, "APB PENABLE must be asserted during OBI RESP phase!")

It is not exactly clear to me why it complains for this, at the beginning I was supposing that defaulted values in the assertion arguments (like __desc = "") translated in Verilator hardcoding that argument to the default, not allowing an instance override. This does not seem to be the case, I think with other IPs (like stream_xbar in the common_cells) this problem does not appear because the assertions are all excluded by default.
This might also be useful in synthesis.

[micprog]

Can we change this to add a define disabling the asserts rather than enabling them? I'd much prefer to have these enabled by default to propagate benefits rather than require users who want it to enable this feature. Adding a define to disable is OK IMO.

[micprog]

After offline discussion, I believe the verilator error you are seeing is caused by a redefinition of the ASSERT macro, not an issue with verilator. Nonetheless agree with adding a disable option as mentioned in the review.

[micprog]

Thanks!