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Make DM support CPU with bus width different from core data width #83

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Make DM support CPU with bus width different from core data width #83

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3 changes: 2 additions & 1 deletion src/dm_mem.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,7 @@
module dm_mem #(
parameter int NrHarts = -1,
parameter int BusWidth = -1,
parameter int Xlen = -1,
parameter logic [NrHarts-1:0] SelectableHarts = -1
)(
input logic clk_i, // Clock
Expand Down Expand Up @@ -58,7 +59,7 @@ module dm_mem #(
);

localparam int HartSelLen = (NrHarts == 1) ? 1 : $clog2(NrHarts);
localparam int MaxAar = (BusWidth == 64) ? 4 : 3;
localparam int MaxAar = (Xlen == 64) ? 4 : 3;
localparam DbgAddressBits = 12;
localparam logic [DbgAddressBits-1:0] DataBase = (dm::DataAddr);
localparam logic [DbgAddressBits-1:0] DataEnd = (dm::DataAddr + 4*dm::DataCount);
Expand Down
2 changes: 2 additions & 0 deletions src/dm_top.sv
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Expand Up @@ -20,6 +20,7 @@
module dm_top #(
parameter int NrHarts = 1,
parameter int BusWidth = 32,
parameter int Xlen = 32,
parameter logic [NrHarts-1:0] SelectableHarts = 1 // Bitmask to select physically available harts for systems
// that don't use hart numbers in a contiguous fashion.

Expand Down Expand Up @@ -183,6 +184,7 @@ module dm_top #(
dm_mem #(
.NrHarts(NrHarts),
.BusWidth(BusWidth),
.Xlen(Xlen),
.SelectableHarts(SelectableHarts)
) i_dm_mem (
.clk_i ( clk_i ),
Expand Down