v1.1.2

Changed

• Removed ternary statement in serial_link_physical for better EDA tool compatibility.

v1.1.1

Changed

• The DDR output data is now muxed by a normal signal instead of a clock signal. Some tools infer a clock gate when a clock signal is used as a mux select signal.

v1.1.0

Changed

• Renamed clock division configuration registers to deliberately introduce breaking changes when using the old incorrect configuration registers.

Fixed

• SW Clock division configuration

v1.0.1

1.0.1 - 2023-03-13

Changed

• Added NoRegCdc parameter to serial_link module to disable the CDC between the RegBus Clock and the System Clock

v1.0.0

Initial release