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Map tc_clk_gating to FPGA primitive for Xilinx FPGAs #38

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Map tc_clk_gating to FPGA primitive for Xilinx FPGAs #38

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16 changes: 14 additions & 2 deletions src/fpga/tc_clk_xilinx.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,6 @@ module tc_clk_buffer (

endmodule

// Disable clock gating on FPGA as it behaves differently than expected
module tc_clk_gating #(
/// This paramaeter is a hint for tool/technology specific mappings of this
/// tech_cell. It indicates wether this particular clk gate instance is
Expand All @@ -44,7 +43,20 @@ module tc_clk_gating #(
output logic clk_o
);

assign clk_o = clk_i;
if (IS_FUNCTIONAL) begin : gen_functional
BUFGCE #(
.CE_TYPE ( "SYNC" ),
.IS_CE_INVERTED ( 1'b0 ),
.IS_I_INVERTED ( 1'b0 ),
.SIM_DEVICE ( "ULTRASCALE" )
) i_clk_gate (
.I ( clk_i ),
.CE ( en_i ),
.O ( clk_o )
);
end else begin : gen_non_functional
assign clk_o = clk_i;
end

endmodule

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