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Prepare qcom-next based on tag 'Linux 6.15-rc7' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git #12

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Merged
shashim-quic merged 5 commits into from
May 30, 2025
Merged

Prepare qcom-next based on tag 'Linux 6.15-rc7' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git #12

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f295cdc
FROMLIST: pinctrl: qcom: correct the ngpios entry for QCS615
yuanjieyang-qualcomm Dec 19, 2024
011df29
FROMLIST: clk: qcom: Add support for Camera Clock Controller on QCS8300
Jan 9, 2025
8310781
FROMGIT: clk: qcom: gcc: Add support for QCS615 GCC clocks
Oct 22, 2024
b93d861
Merge remote-tracking branch tech/bsp/clk into qcom-next
sgaud-quic May 24, 2025
db92190
Merge remote-tracking branch tech/bsp/pinctrl into qcom-next
sgaud-quic May 24, 2025
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8 changes: 8 additions & 0 deletions drivers/clk/qcom/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -519,6 +519,14 @@ config QCS_GCC_8300
QCS8300 devices.
Say Y if you want to use peripheral devices such as UART,
SPI, I2C, USB, SD/UFS, PCIe etc.
config QCS_GCC_615
tristate "QCS615 Global Clock Controller"
depends on ARM64 || COMPILE_TEST
select QCOM_GDSC
help
Support for the global clock controller on QCS615 devices.
Say Y if you want to use multimedia devices or peripheral
devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc.

config QCS_GCC_615
tristate "QCS615 Global Clock Controller"
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1 change: 1 addition & 0 deletions drivers/clk/qcom/Makefile
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Expand Up @@ -76,6 +76,7 @@ obj-$(CONFIG_QCM_DISPCC_2290) += dispcc-qcm2290.o
obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o
obj-$(CONFIG_QCS_GCC_615) += gcc-qcs615.o
obj-$(CONFIG_QCS_GCC_8300) += gcc-qcs8300.o
obj-$(CONFIG_QCS_GCC_615) += gcc-qcs615.o
obj-$(CONFIG_QCS_Q6SSTOP_404) += q6sstop-qcs404.o
obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o
obj-$(CONFIG_QDU_ECPRICC_1000) += ecpricc-qdu1000.o
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103 changes: 98 additions & 5 deletions drivers/clk/qcom/camcc-sa8775p.c
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Expand Up @@ -10,7 +10,7 @@
#include <linux/pm_runtime.h>
#include <linux/regmap.h>

#include <dt-bindings/clock/qcom,sa8775p-camcc.h>
#include <dt-bindings/clock/qcom,qcs8300-camcc.h>

#include "clk-alpha-pll.h"
#include "clk-branch.h"
Expand Down Expand Up @@ -1681,6 +1681,24 @@ static struct clk_branch cam_cc_sm_obs_clk = {
},
};

static struct clk_branch cam_cc_titan_top_accu_shift_clk = {
.halt_reg = 0x131f0,
.halt_check = BRANCH_HALT_VOTED,
.clkr = {
.enable_reg = 0x131f0,
.enable_mask = BIT(0),
.hw.init = &(const struct clk_init_data) {
.name = "cam_cc_titan_top_accu_shift_clk",
.parent_hws = (const struct clk_hw*[]) {
&cam_cc_xo_clk_src.clkr.hw,
},
.num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
.ops = &clk_branch2_ops,
},
},
};

static struct gdsc cam_cc_titan_top_gdsc = {
.gdscr = 0x131bc,
.en_rest_wait_val = 0x2,
Expand Down Expand Up @@ -1775,6 +1793,7 @@ static struct clk_regmap *cam_cc_sa8775p_clocks[] = {
[CAM_CC_SLEEP_CLK_SRC] = &cam_cc_sleep_clk_src.clkr,
[CAM_CC_SLOW_AHB_CLK_SRC] = &cam_cc_slow_ahb_clk_src.clkr,
[CAM_CC_SM_OBS_CLK] = &cam_cc_sm_obs_clk.clkr,
[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] = NULL,
[CAM_CC_XO_CLK_SRC] = &cam_cc_xo_clk_src.clkr,
[CAM_CC_QDSS_DEBUG_XO_CLK] = &cam_cc_qdss_debug_xo_clk.clkr,
};
Expand Down Expand Up @@ -1811,6 +1830,7 @@ static const struct qcom_cc_desc cam_cc_sa8775p_desc = {
};

static const struct of_device_id cam_cc_sa8775p_match_table[] = {
{ .compatible = "qcom,qcs8300-camcc" },
{ .compatible = "qcom,sa8775p-camcc" },
{ }
};
Expand Down Expand Up @@ -1841,10 +1861,83 @@ static int cam_cc_sa8775p_probe(struct platform_device *pdev)
clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);
clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config);

/* Keep some clocks always enabled */
qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */
qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */
if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-camcc")) {
cam_cc_camnoc_axi_clk_src.cmd_rcgr = 0x13154;
cam_cc_camnoc_axi_clk.halt_reg = 0x1316c;
cam_cc_camnoc_axi_clk.clkr.enable_reg = 0x1316c;
cam_cc_camnoc_dcd_xo_clk.halt_reg = 0x13174;
cam_cc_camnoc_dcd_xo_clk.clkr.enable_reg = 0x13174;

cam_cc_csi0phytimer_clk_src.cmd_rcgr = 0x15054;
cam_cc_csi1phytimer_clk_src.cmd_rcgr = 0x15078;
cam_cc_csi2phytimer_clk_src.cmd_rcgr = 0x15098;
cam_cc_csid_clk_src.cmd_rcgr = 0x13134;

cam_cc_mclk0_clk_src.cmd_rcgr = 0x15000;
cam_cc_mclk1_clk_src.cmd_rcgr = 0x1501c;
cam_cc_mclk2_clk_src.cmd_rcgr = 0x15038;

cam_cc_fast_ahb_clk_src.cmd_rcgr = 0x13104;
cam_cc_slow_ahb_clk_src.cmd_rcgr = 0x1311c;
cam_cc_xo_clk_src.cmd_rcgr = 0x131b8;
cam_cc_sleep_clk_src.cmd_rcgr = 0x131d4;

cam_cc_core_ahb_clk.halt_reg = 0x131b4;
cam_cc_core_ahb_clk.clkr.enable_reg = 0x131b4;

cam_cc_cpas_ahb_clk.halt_reg = 0x130f4;
cam_cc_cpas_ahb_clk.clkr.enable_reg = 0x130f4;
cam_cc_cpas_fast_ahb_clk.halt_reg = 0x130fc;
cam_cc_cpas_fast_ahb_clk.clkr.enable_reg = 0x130fc;

cam_cc_csi0phytimer_clk.halt_reg = 0x1506c;
cam_cc_csi0phytimer_clk.clkr.enable_reg = 0x1506c;
cam_cc_csi1phytimer_clk.halt_reg = 0x15090;
cam_cc_csi1phytimer_clk.clkr.enable_reg = 0x15090;
cam_cc_csi2phytimer_clk.halt_reg = 0x150b0;
cam_cc_csi2phytimer_clk.clkr.enable_reg = 0x150b0;
cam_cc_csid_clk.halt_reg = 0x1314c;
cam_cc_csid_clk.clkr.enable_reg = 0x1314c;
cam_cc_csid_csiphy_rx_clk.halt_reg = 0x15074;
cam_cc_csid_csiphy_rx_clk.clkr.enable_reg = 0x15074;
cam_cc_csiphy0_clk.halt_reg = 0x15070;
cam_cc_csiphy0_clk.clkr.enable_reg = 0x15070;
cam_cc_csiphy1_clk.halt_reg = 0x15094;
cam_cc_csiphy1_clk.clkr.enable_reg = 0x15094;
cam_cc_csiphy2_clk.halt_reg = 0x150b4;
cam_cc_csiphy2_clk.clkr.enable_reg = 0x150b4;

cam_cc_mclk0_clk.halt_reg = 0x15018;
cam_cc_mclk0_clk.clkr.enable_reg = 0x15018;
cam_cc_mclk1_clk.halt_reg = 0x15034;
cam_cc_mclk1_clk.clkr.enable_reg = 0x15034;
cam_cc_mclk2_clk.halt_reg = 0x15050;
cam_cc_mclk2_clk.clkr.enable_reg = 0x15050;
cam_cc_qdss_debug_xo_clk.halt_reg = 0x1319c;
cam_cc_qdss_debug_xo_clk.clkr.enable_reg = 0x1319c;

cam_cc_titan_top_gdsc.gdscr = 0x131a0;

cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK] = NULL;
cam_cc_sa8775p_clocks[CAM_CC_CCI_3_CLK_SRC] = NULL;
cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK] = NULL;
cam_cc_sa8775p_clocks[CAM_CC_CSI3PHYTIMER_CLK_SRC] = NULL;
cam_cc_sa8775p_clocks[CAM_CC_CSIPHY3_CLK] = NULL;
cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK] = NULL;
cam_cc_sa8775p_clocks[CAM_CC_MCLK3_CLK_SRC] = NULL;
cam_cc_sa8775p_clocks[CAM_CC_TITAN_TOP_ACCU_SHIFT_CLK] =
&cam_cc_titan_top_accu_shift_clk.clkr;

/* Keep some clocks always enabled */
qcom_branch_set_clk_en(regmap, 0x13178); /* CAM_CC_CAMNOC_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x131d0); /* CAM_CC_GDSC_CLK */
qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_SLEEP_CLK */
} else {
/* Keep some clocks always enabled */
qcom_branch_set_clk_en(regmap, 0x13194); /* CAM_CC_CAMNOC_XO_CLK */
qcom_branch_set_clk_en(regmap, 0x131ec); /* CAM_CC_GDSC_CLK */
qcom_branch_set_clk_en(regmap, 0x13208); /* CAM_CC_SLEEP_CLK */
}

ret = qcom_cc_really_probe(&pdev->dev, &cam_cc_sa8775p_desc, regmap);

Expand Down
2 changes: 1 addition & 1 deletion drivers/pinctrl/qcom/pinctrl-qcs615.c
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Expand Up @@ -1062,7 +1062,7 @@ static const struct msm_pinctrl_soc_data qcs615_tlmm = {
.nfunctions = ARRAY_SIZE(qcs615_functions),
.groups = qcs615_groups,
.ngroups = ARRAY_SIZE(qcs615_groups),
.ngpios = 123,
.ngpios = 124,
.tiles = qcs615_tiles,
.ntiles = ARRAY_SIZE(qcs615_tiles),
.wakeirq_map = qcs615_pdc_map,
Expand Down
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