raspberrypi · will-v-pi · Dec 12, 2024 · Sep 1, 2025 · Sep 4, 2025 · Sep 4, 2025
diff --git a/pico_sdk_version.cmake b/pico_sdk_version.cmake
@@ -10,7 +10,7 @@ if (NOT DEFINED PICO_SDK_VERSION_MAJOR)
     set(PICO_SDK_VERSION_REVISION 1)
     # PICO_BUILD_DEFINE: PICO_SDK_VERSION_PRE_RELEASE_ID, Optional SDK pre-release version identifier, default=Current SDK pre-release identifier, type=string, group=pico_base
     # PICO_CMAKE_CONFIG: PICO_SDK_VERSION_PRE_RELEASE_ID, Optional SDK pre-release version identifier, default=Current SDK pre-release identifier, type=string, group=pico_base
-    set(PICO_SDK_VERSION_PRE_RELEASE_ID develop)
+    set(PICO_SDK_VERSION_PRE_RELEASE_ID xip-sram)
 endif()
 
 # PICO_BUILD_DEFINE: PICO_SDK_VERSION_STRING, SDK version string, type=string, default=Current SDK version string, group=pico_base

diff --git a/src/rp2_common/hardware_flash/flash.c b/src/rp2_common/hardware_flash/flash.c
@@ -10,6 +10,7 @@
 #if PICO_RP2040
 #include "hardware/structs/io_qspi.h"
 #include "hardware/structs/ssi.h"
+#include "hardware/structs/xip.h"
 #else
 #include "hardware/structs/qmi.h"
 #include "hardware/regs/otp_data.h"
@@ -127,7 +128,9 @@ static void __no_inline_not_in_flash_func(flash_rp2350_restore_qmi_cs1)(const fl
 
 
 typedef struct flash_hardware_save_state {
-#if !PICO_RP2040
+#if PICO_RP2040
+    uint32_t xip_ctrl;
+#else
     flash_rp2350_qmi_save_state_t qmi_save;
 #endif
     uint32_t qspi_pads[count_of(pads_qspi_hw->io)];
@@ -139,7 +142,9 @@ static void __no_inline_not_in_flash_func(flash_save_hardware_state)(flash_hardw
     for (size_t i = 0; i < count_of(pads_qspi_hw->io); ++i) {
         state->qspi_pads[i] = pads_qspi_hw->io[i];
     }
-#if !PICO_RP2040
+#if PICO_RP2040
+    state->xip_ctrl = xip_ctrl_hw->ctrl;
+#else
     flash_rp2350_save_qmi_cs1(&state->qmi_save);
 #endif
 }
@@ -148,7 +153,9 @@ static void __no_inline_not_in_flash_func(flash_restore_hardware_state)(flash_ha
     for (size_t i = 0; i < count_of(pads_qspi_hw->io); ++i) {
         pads_qspi_hw->io[i] = state->qspi_pads[i];
     }
-#if !PICO_RP2040
+#if PICO_RP2040
+    xip_ctrl_hw->ctrl = state->xip_ctrl;
+#else
     // Tail call!
     flash_rp2350_restore_qmi_cs1(&state->qmi_save);
 #endif

diff --git a/src/rp2_common/hardware_sync_spin_lock/include/hardware/sync/spin_lock.h b/src/rp2_common/hardware_sync_spin_lock/include/hardware/sync/spin_lock.h
@@ -10,7 +10,7 @@
 #include "pico.h"
 #include "hardware/sync.h"
 
-// PICO_CONFIG: PICO_USE_SW_SPIN_LOCKS, Use software implementation for spin locks, type=bool, default=1 on RP2350 due to errata, group=hardware_sync
+// PICO_CONFIG: PICO_USE_SW_SPIN_LOCKS, Use software implementation for spin locks, type=bool, default=1 on RP2350 due to errata E2, group=hardware_sync
 #ifndef PICO_USE_SW_SPIN_LOCKS
 #if PICO_RP2350
 #define PICO_USE_SW_SPIN_LOCKS 1
@@ -19,53 +19,93 @@
 
 // PICO_CONFIG: PICO_SPINLOCK_ID_IRQ, Spinlock ID for IRQ protection, min=0, max=31, default=9, group=hardware_sync
 #ifndef PICO_SPINLOCK_ID_IRQ
+#if PICO_RP2350 && !PICO_USE_SW_SPIN_LOCKS
+#define PICO_SPINLOCK_ID_IRQ 5
+#else
 #define PICO_SPINLOCK_ID_IRQ 9
 #endif
+#endif
 
 // PICO_CONFIG: PICO_SPINLOCK_ID_TIMER, Spinlock ID for Timer protection, min=0, max=31, default=10, group=hardware_sync
 #ifndef PICO_SPINLOCK_ID_TIMER
+#if PICO_RP2350 && !PICO_USE_SW_SPIN_LOCKS
+#define PICO_SPINLOCK_ID_TIMER 6
+#else
 #define PICO_SPINLOCK_ID_TIMER 10
 #endif
+#endif
 
 // PICO_CONFIG: PICO_SPINLOCK_ID_HARDWARE_CLAIM, Spinlock ID for Hardware claim protection, min=0, max=31, default=11, group=hardware_sync
 #ifndef PICO_SPINLOCK_ID_HARDWARE_CLAIM
+#if PICO_RP2350 && !PICO_USE_SW_SPIN_LOCKS
+#define PICO_SPINLOCK_ID_HARDWARE_CLAIM 7
+#else
 #define PICO_SPINLOCK_ID_HARDWARE_CLAIM 11
 #endif
+#endif
 
 // PICO_CONFIG: PICO_SPINLOCK_ID_RAND, Spinlock ID for Random Number Generator, min=0, max=31, default=12, group=hardware_sync
 #ifndef PICO_SPINLOCK_ID_RAND
+#if PICO_RP2350 && !PICO_USE_SW_SPIN_LOCKS
+#define PICO_SPINLOCK_ID_RAND 10
+#else
 #define PICO_SPINLOCK_ID_RAND 12
 #endif
+#endif
 
 // PICO_CONFIG: PICO_SPINLOCK_ID_ATOMIC, Spinlock ID for atomics, min=0, max=31, default=13, group=hardware_sync
 #ifndef PICO_SPINLOCK_ID_ATOMIC
+#if PICO_RP2350 && !PICO_USE_SW_SPIN_LOCKS
+#define PICO_SPINLOCK_ID_ATOMIC 11
+#else
 #define PICO_SPINLOCK_ID_ATOMIC 13
 #endif
+#endif
 
 // PICO_CONFIG: PICO_SPINLOCK_ID_OS1, First Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=14, group=hardware_sync
 #ifndef PICO_SPINLOCK_ID_OS1
+#if PICO_RP2350 && !PICO_USE_SW_SPIN_LOCKS
+#define PICO_SPINLOCK_ID_OS1 18
+#else
 #define PICO_SPINLOCK_ID_OS1 14
 #endif
+#endif
 
 // PICO_CONFIG: PICO_SPINLOCK_ID_OS2, Second Spinlock ID reserved for use by low level OS style software, min=0, max=31, default=15, group=hardware_sync
 #ifndef PICO_SPINLOCK_ID_OS2
+#if PICO_RP2350 && !PICO_USE_SW_SPIN_LOCKS
+#define PICO_SPINLOCK_ID_OS2 19
+#else
 #define PICO_SPINLOCK_ID_OS2 15
 #endif
+#endif
 
 // PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_FIRST, Lowest Spinlock ID in the 'striped' range, min=0, max=31, default=16, group=hardware_sync
 #ifndef PICO_SPINLOCK_ID_STRIPED_FIRST
+#if PICO_RP2350 && !PICO_USE_SW_SPIN_LOCKS
+#define PICO_SPINLOCK_ID_STRIPED_FIRST 20
+#else
 #define PICO_SPINLOCK_ID_STRIPED_FIRST 16
 #endif
+#endif
 
 // PICO_CONFIG: PICO_SPINLOCK_ID_STRIPED_LAST, Highest Spinlock ID in the 'striped' range, min=0, max=31, default=23, group=hardware_sync
 #ifndef PICO_SPINLOCK_ID_STRIPED_LAST
+#if PICO_RP2350 && !PICO_USE_SW_SPIN_LOCKS
+#define PICO_SPINLOCK_ID_STRIPED_LAST 25
+#else
 #define PICO_SPINLOCK_ID_STRIPED_LAST 23
 #endif
+#endif
 
 // PICO_CONFIG: PICO_SPINLOCK_ID_CLAIM_FREE_FIRST, Lowest Spinlock ID in the 'claim free' range, min=0, max=31, default=24, group=hardware_sync
 #ifndef PICO_SPINLOCK_ID_CLAIM_FREE_FIRST
+#if PICO_RP2350 && !PICO_USE_SW_SPIN_LOCKS
+#define PICO_SPINLOCK_ID_CLAIM_FREE_FIRST 26
+#else
 #define PICO_SPINLOCK_ID_CLAIM_FREE_FIRST 24
 #endif
+#endif
 
 #ifdef PICO_SPINLOCK_ID_CLAIM_FREE_END
 #warning PICO_SPINLOCK_ID_CLAIM_FREE_END has been renamed to PICO_SPINLOCK_ID_CLAIM_FREE_LAST

diff --git a/src/rp2_common/pico_crt0/crt0.S b/src/rp2_common/pico_crt0/crt0.S
@@ -11,6 +11,7 @@
 
 #include "hardware/regs/addressmap.h"
 #include "hardware/regs/sio.h"
+#include "hardware/regs/xip.h"
 #include "pico/binary_info/defs.h"
 #include "boot/picobin.h"
 #include "pico/bootrom.h"
@@ -20,6 +21,11 @@
 #define PICO_CRT0_NEAR_CALLS 0
 #endif
 
+// PICO_CONFIG: PICO_CRT0_NO_DATA_COPY, Whether crt0 should perform the data copies - usually copying from flash into sram, default=1 for no_flash builds, 0 otherwise, type=bool, group=pico_crt0
+#ifndef PICO_CRT0_NO_DATA_COPY
+#define PICO_CRT0_NO_DATA_COPY PICO_NO_FLASH
+#endif
+
 #ifdef NDEBUG
 #ifndef COLLAPSE_IRQS
 #define COLLAPSE_IRQS
@@ -457,6 +463,14 @@ hold_non_core0_in_bootrom:
     b _enter_vtable_in_r0
 1:
 
+#if PICO_RP2040 && PICO_USE_XIP_CACHE_AS_RAM
+_disable_xip_cache:
+    // Disable the XIP cache on RP2040 making its SRAM available for use
+    ldr r0, =(REG_ALIAS_CLR_BITS + XIP_CTRL_BASE + XIP_CTRL_OFFSET)
+    movs r1, #XIP_CTRL_EN_BITS
+    str r1, [r0]
+#endif
+
 #if !PICO_RP2040 && PICO_EMBED_XIP_SETUP && !PICO_NO_FLASH
     // Execute boot2 on the core 0 stack (it also gets copied into BOOTRAM due
     // to inclusion in the data copy table below). Note the reference
@@ -477,7 +491,7 @@ _call_xip_setup:
 
     // In a NO_FLASH binary, don't perform .data etc copy, since it's loaded
     // in-place by the SRAM load. Still need to clear .bss
-#if !PICO_NO_FLASH
+#if !PICO_CRT0_NO_DATA_COPY
     adr r4, data_cpy_table
 
     // assume there is at least one entry
@@ -522,11 +536,21 @@ platform_entry: // symbol for stack traces
     b 1b
 
 
-#if !PICO_NO_FLASH
+#if !PICO_CRT0_NO_DATA_COPY
+#if PICO_NO_FLASH
+data_cpy:
+    // skip copies with same source and destination
+    cmp r1, r2
+    bne data_cpy_start
+    bx lr
+#else
+    // go straight into the copy
+    #define data_cpy_start data_cpy
+#endif
 data_cpy_loop:
     ldm r1!, {r0}
     stm r2!, {r0}
-data_cpy:
+data_cpy_start:
     cmp r2, r3
     blo data_cpy_loop
     bx lr
@@ -560,6 +584,10 @@ data_cpy_table:
 .word __scratch_y_start__
 .word __scratch_y_end__
 
+#ifdef PICO_DATA_COPY_EXTRA_SECTIONS_FILE
+#include PICO_DATA_COPY_EXTRA_SECTIONS_FILE
+#endif
+
 .word 0 // null terminator
 
 // ----------------------------------------------------------------------------

diff --git a/src/rp2_common/pico_crt0/crt0_riscv.S b/src/rp2_common/pico_crt0/crt0_riscv.S
@@ -30,6 +30,10 @@
 #define PICO_CRT0_INCLUDE_PICOBIN_END_BLOCK (PICO_CRT0_INCLUDE_PICOBIN_BLOCK && !PICO_NO_FLASH)
 #endif
 
+#ifndef PICO_CRT0_NO_DATA_COPY
+#define PICO_CRT0_NO_DATA_COPY PICO_NO_FLASH
+#endif
+
 // If vectors are in RAM, we put them in the .data section, so that they are
 // preloaded by _reset_handler (assuming this is not a loaded-in-place
 // binary).
@@ -340,7 +344,7 @@ _call_xip_setup:
 
     // In a NO_FLASH binary, don't perform .data etc copy, since it's loaded
     // in-place by the SRAM load. Still need to clear .bss
-#if !PICO_NO_FLASH
+#if !PICO_CRT0_NO_DATA_COPY
     la a4, data_cpy_table
 
     // assume there is at least one entry
@@ -379,14 +383,25 @@ platform_entry: // symbol for stack traces
     ebreak
     j 1b
 
+#if !PICO_CRT0_NO_DATA_COPY
+#if PICO_NO_FLASH
+data_cpy:
+    // skip copies with same source and destination
+    bne a0, a1, data_cpy_start
+    ret
+#else
+    // go straight into the copy
+    #define data_cpy_start data_cpy
+#endif
 data_cpy_loop:
     lw a0, (a1)
     sw a0, (a2)
     addi a1, a1, 4
     addi a2, a2, 4
-data_cpy:
+data_cpy_start:
     bltu a2, a3, data_cpy_loop
     ret
+#endif
 
 .align 2
 data_cpy_table:
@@ -412,6 +427,10 @@ data_cpy_table:
 .word __scratch_y_start__
 .word __scratch_y_end__
 
+#ifdef PICO_DATA_COPY_EXTRA_SECTIONS_FILE
+#include PICO_DATA_COPY_EXTRA_SECTIONS_FILE
+#endif
+
 .word 0 // null terminator
 
 // ----------------------------------------------------------------------------

diff --git a/src/rp2_common/pico_crt0/embedded_start_block.inc.S b/src/rp2_common/pico_crt0/embedded_start_block.inc.S
@@ -12,6 +12,10 @@
 #endif
 #endif
 
+#ifndef PICO_CRT0_PIN_XIP_SRAM
+#define PICO_CRT0_PIN_XIP_SRAM PICO_USE_XIP_CACHE_AS_RAM
+#endif
+
 #ifndef PICO_CRT0_INCLUDE_PICOBIN_ENTRY_POINT_ITEM
 // On RISC-V the default entry point from bootrom is the start of the binary, but
 // we have our vtable at the start, so we must include an entry point
@@ -104,6 +108,16 @@ embedded_block:
 .word __vectors
 #endif
 
+#if PICO_CRT0_PIN_XIP_SRAM
+.byte PICOBIN_BLOCK_ITEM_LOAD_MAP
+.byte 0x04 // word size
+.byte 0 // pad
+.byte 0x01 // number of entries
+.word 0 // clear
+.word XIP_SRAM_BASE
+.word 0 // size
+#endif
+
 .byte PICOBIN_BLOCK_ITEM_2BS_LAST
 .hword (embedded_block_end - embedded_block - 16 ) / 4 // total size of all
 .byte 0

diff --git a/src/rp2_common/pico_crt0/rp2040/memmap_blocked_ram.ld b/src/rp2_common/pico_crt0/rp2040/memmap_blocked_ram.ld
@@ -27,6 +27,7 @@ MEMORY
     RAM(rwx) : ORIGIN =  0x21000000, LENGTH = 256k
     SCRATCH_X(rwx) : ORIGIN = 0x20040000, LENGTH = 4k
     SCRATCH_Y(rwx) : ORIGIN = 0x20041000, LENGTH = 4k
+
 }
 
 ENTRY(_entry_point)
@@ -149,6 +150,8 @@ SECTIONS
         *(.uninitialized_data*)
     } > RAM
 
+
+
     .data : {
         __data_start__ = .;
         *(vtable)