Add qemu CI

[KushalMeghani1644]

This PR adds a Github Actions workflow to build and execute RISC-V examples on QEMU, enabling detection of runtime bugs that static compilation checks may miss.

This PR addresses issue #311

[KushalMeghani1644]

ugh, I shall work on this more... thus I am making it a draft.

[KushalMeghani1644]

Hola @romancardenas I tried to add QEMU CI here but things are getting way harder, I have done multiple fixes but I just want to make sure the fact that am I even going in the right direction? (sorry for the noise in this PR btw)

[romancardenas]

Adding QEMU to the CI is not that easy. You must create working examples that produce an output that you can then check with something like xtasks. Check how rtic does this.

You must find a set of "illustrative" targets (e.g., e310x for riscv32imc, something else for riscv64gc...) and run examples there.

Again, it is quite a complex task, and I suggest you to leave it until you get more expertise on these subjects.

[KushalMeghani1644]

I see! Thanks for helping me out!! And I do agree/understand that setting up QEMU ci is very complex, but I feel it will be valuable challenge to give a shot. Even if it takes time, I think it would be fun learning experience! Appreciate your guidance!

[romancardenas]

Good luck with it! RTIC has a great CI that runs tests on Arm and RISC-V. You can learn a lot from their project. Also, you can check how the esp-rs folks do it.

[KushalMeghani1644]

Thanks alot for your guidance! I appreciate it alot.

[KushalMeghani1644]

HI @romancardenas I am sorry to ping you again & again... I tried a-lot to mirror the RTIC QEMU CI here and seeing the mixed results here... I need your help for further fixes and guidance for what I shall do next?

[KushalMeghani1644]

well @romancardenas I did a re-check of the RTIC crate's QEMU CI... and seems like it was easily fixable... now I just need your guidance upon what shall I change/update or what's wrong and what not! Thanks for your review and sorry for the disturbances.