ECOS Chip Compiler (ECC)

Open-Source Chip Design Automation Solution

Overview

ECOS Chip Compiler is an open-source chip design automation solution that integrates EDA tools (Yosys, ECC-Tools, KLayout) to achieve complete RTL-to-GDS design flow. Developed and maintained by the ECOS Team.

The GUI (ECOS Studio) has been moved to the ecos-studio repo.

How to use:

• CLI (cli) - Command-line flow execution
• Python API - Use chipcompiler as a library

Quick Start

CLI Flow Runner

Use nix run .#cli -- ... to create a workspace and run the full RTL2GDS flow directly.

nix run .#cli -- --workspace ./ws \
                --rtl ./rtl/top.v \
                --design top \
                --top top \
                --clock clk \
                --pdk-root /path/to/ics55
nix run .#cli -- --workspace ./ws \
                --rtl ./rtl/filelist.f \
                --design top \
                --top top \
                --clock clk \
                --pdk-root /path/to/ics55 \
                --freq 200

Features

• Complete RTL-to-GDS Flow - Synthesis, placement, routing, timing optimization
• Open-Source EDA Integration - Yosys (synthesis), ECC-Tools (P&R), KLayout (viewer)
• CLI Automation - Scriptable flow execution from command line
• Portable Deployment - Nix or standalone builds

🛠️ Integrated Tools

Tool	Purpose	Status
Yosys	RTL Synthesis	✅
ECC-Tools	Physical Design (P&R)	✅
KLayout	Layout Viewer	🚧

Documentation

• Documentation Index - Complete navigation
• Architecture - System design and patterns
• Development Guide - Setup and workflows
• Examples - Usage examples

Contributing

Contributions welcome! See Development Guide for setup instructions.

Acknowledgments

Special thanks to these open-source projects:

• Yosys - RTL Synthesis
• ECC-Tools - Physical Design Backend
• KLayout - Layout Viewer
• nixpkgs - A collection of Nix packages

Built by the ECOS Team

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